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Enabled internal pullup for CML SYSREF outputs, otherwise there is no signal on them. 

Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
This commit is contained in:
Paweł Kulik 2019-12-06 15:41:19 +01:00 committed by Sébastien Bourdeauducq
parent 7098854b0f
commit 14e250c78f
1 changed files with 2 additions and 2 deletions
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4
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -150,9 +150,9 @@ pub mod hmc7043 {
// enabled, divider, output config, is sysref // enabled, divider, output config, is sysref
const OUTPUT_CONFIG: [(bool, u16, u8, bool); 14] = [ const OUTPUT_CONFIG: [(bool, u16, u8, bool); 14] = [
(true, DAC_CLK_DIV, 0x08, false), // 0: DAC1_CLK (true, DAC_CLK_DIV, 0x08, false), // 0: DAC1_CLK
(true, SYSREF_DIV, 0x00, true), // 1: DAC1_SYSREF (true, SYSREF_DIV, 0x01, true), // 1: DAC1_SYSREF
(true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK (true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK
(true, SYSREF_DIV, 0x00, true), // 3: DAC0_SYSREF (true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF
(true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0 (true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0
(true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1 (true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
(false, 0, 0x10, false), // 6: unused (false, 0, 0x10, false), // 6: unused