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drtio: aux controller fixes
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@ -111,11 +111,17 @@ class Receiver(Module, AutoCSR):
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self.submodules += converter
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# when continuously drained, the Converter accepts data continuously
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frame_r = Signal()
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self.sync.rtio_rx += [
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converter.sink.stb.eq(link_layer.rx_aux_stb & link_layer.rx_aux_frame),
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If(link_layer.rx_aux_stb,
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frame_r.eq(link_layer.rx_aux_frame),
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converter.sink.data.eq(link_layer.rx_aux_data)
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)
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]
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self.comb += [
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converter.sink.stb.eq(link_layer.rx_aux_stb & frame_r),
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converter.sink.eop.eq(converter.sink.stb & ~link_layer.rx_aux_frame)
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]
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self.comb += converter.sink.eop.eq(link_layer.rx_aux_stb & ~link_layer.rx_aux_frame)
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mem_port = self.mem.get_port(write_capable=True, clock_domain="rtio_rx")
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self.specials += mem_port
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@ -136,7 +142,7 @@ class Receiver(Module, AutoCSR):
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signal_frame = PulseSynchronizer("rtio_rx", "sys")
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frame_ack = PulseSynchronizer("sys", "rtio_rx")
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signal_error = PulseSynchronizer("rtio_rx", "sys")
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self.submodules += signal_frame, signal_error
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self.submodules += signal_frame, frame_ack, signal_error
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self.sync += [
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If(self.aux_rx_present.re, self.aux_rx_present.w.eq(0)),
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If(signal_frame.o, self.aux_rx_present.w.eq(1)),
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