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mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00

devices/rtio_core: set OE, implement gate/count

This commit is contained in:
Sebastien Bourdeauducq 2014-09-15 22:48:22 +08:00
parent 8bf7b27a89
commit 140b4eb594

View File

@ -1,7 +1,7 @@
from artiq.language.core import *
class RTIOOut(AutoContext):
class _RTIOBase(AutoContext):
parameters = "channel"
def build(self):
@ -10,6 +10,10 @@ class RTIOOut(AutoContext):
kernel_attr = "previous_timestamp previous_value"
@kernel
def _set_oe(self, oe):
syscall("rtio_oe", self.channel, oe)
@kernel
def _set_value(self, value):
if self.previous_value != value:
@ -20,6 +24,12 @@ class RTIOOut(AutoContext):
self.previous_timestamp = now()
self.previous_value = value
class RTIOOut(_RTIOBase):
def build(self):
_RTIOBase.build(self)
self._set_oe(1)
@kernel
def sync(self):
syscall("rtio_sync", self.channel)
@ -39,13 +49,32 @@ class RTIOOut(AutoContext):
self.off()
class RTIOCounter(AutoContext):
parameters = "channel"
class RTIOCounter(_RTIOBase):
def build(self):
_RTIOBase.build(self)
self._set_oe(0)
@kernel
def count_rising(self, duration):
pass
self._set_value(1)
delay(duration)
self._set_value(0)
@kernel
def count_falling(self, duration):
self._set_value(2)
delay(duration)
self._set_value(0)
@kernel
def count_both_edges(self, duration):
self._set_value(3)
delay(duration)
self._set_value(0)
@kernel
def sync(self):
return 42
count = 0
while syscall("rtio_get", self.channel) >= 0:
count += 1
return count