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Clean up (doc-strings etc.) in artiq.coredevice.urukul
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parent
ef7f730ea9
commit
1204c15351
@ -142,6 +142,13 @@ class _DummySync:
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class CPLDVersionManager(ABC):
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"""
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Base class for managing CPLD version-specific configurations.
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Subclasses should implement the required methods based on the specific
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version of the CPLD being used.
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"""
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@abstractmethod
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@kernel
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def cfg_write(self, cpld, cfg):
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@ -167,19 +174,27 @@ class CPLDVersionManager(ABC):
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def set_profile(self, cpld, channel, profile):
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pass
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@kernel
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def _configure_bit(self, cpld, bit_offset: TInt32, channel: TInt32, on: TBool):
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pass
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@kernel
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def _configure_all_bits(self, cpld, bit_offset: TInt32, state: TInt32):
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pass
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@kernel
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def cfg_mask_nu(self, cpld, channel: TInt32, on: TBool):
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pass
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@kernel
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def cfg_mask_nu_all(self, cpld, state: TInt32):
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pass
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def _not_implemented(self, *args, **kwargs):
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raise NotImplementedError(
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"This function is not implemented for this Urukul version."
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)
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@kernel
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def _configure_bit(self, cpld, bit_offset: TInt32, channel: TInt32, on: TBool):
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self._not_implemented()
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@kernel
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def _configure_all_bits(self, cpld, bit_offset: TInt32, state: TInt32):
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self._not_implemented()
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@kernel
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def cfg_att_en(self, cpld, channel: TInt32, on: TBool):
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self._not_implemented()
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@ -212,16 +227,14 @@ class CPLDVersionManager(ABC):
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def cfg_drhold_all(self, cpld, state: TInt32):
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self._not_implemented()
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@kernel
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def cfg_mask_nu(self, cpld, channel: TInt32, on: TBool):
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self._not_implemented()
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@kernel
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def cfg_mask_nu_all(self, cpld, state: TInt32):
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self._not_implemented()
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class ProtoRev8(CPLDVersionManager):
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"""
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Implementation of the CPLD for Urkul ProtoRev8.
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This class extends `CPLDVersionManager` and provides methods to configure
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and interact with the ProtoRev8 version of the CPLD.
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"""
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# ProtoRev8 CFG configuration register bit offsets
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CFG_IO_UPDATE = 12
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@ -297,10 +310,9 @@ class ProtoRev8(CPLDVersionManager):
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@kernel
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def init(self, cpld):
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"""Initialize and detect Urukul.
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"""Initialize Urukul with ProtoRev8.
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Resets the DDS I/O interface and verifies correct CPLD gateware
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version.
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Resets the DDS I/O interface.
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Does not pulse the DDS ``MASTER_RESET`` as that confuses the AD9910.
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"""
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cfg = cpld.cfg_reg
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@ -325,14 +337,64 @@ class ProtoRev8(CPLDVersionManager):
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The PROFILE pins are common to all four DDS channels.
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:param channel: Channel index (0-3). Unused (here for backwards compatability).
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:param profile: PROFILE pins in numeric representation (0-7).
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"""
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cfg = cpld.cfg_reg & ~(7 << CFG_PROFILE)
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cfg |= (profile & 7) << CFG_PROFILE
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cpld.cfg_write(cfg)
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@kernel
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def _configure_bit(self, cpld, bit_offset: TInt32, channel: TInt32, on: TBool):
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"""Configure a single bit in the configuration register.
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:param bit_offset: Base bit offset for the configuration type
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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c = cpld.cfg_reg
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if on:
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c |= 1 << (bit_offset + channel)
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else:
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c &= ~(1 << (bit_offset + channel))
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cpld.cfg_write(c)
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@kernel
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def _configure_all_bits(self, cpld, bit_offset: TInt32, state: TInt32):
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"""Configure all four bits at a specific bit offset in the configuration register.
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:param bit_offset: bit offset for the configuration bits
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:param state: State as a 4-bit integer
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"""
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cpld.cfg_write(
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(cpld.cfg_reg & ~(0xF << bit_offset)) | (int64(state) << bit_offset)
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)
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@kernel
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def cfg_mask_nu(self, cpld, channel: TInt32, on: TBool):
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"""Configure the MASK_NU bit for the given channel in the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev8.CFG_MASK_NU, channel, on)
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@kernel
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def cfg_mask_nu_all(self, cpld, state: TInt32):
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"""Configure all four MASK_NU bits in the configuration register.
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:param state: MASK_NU state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev8.CFG_MASK_NU, state)
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class ProtoRev9(CPLDVersionManager):
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"""
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Implementation of the CPLD for Urkul ProtoRev9.
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This class extends `CPLDVersionManager` and provides methods to configure
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and interact with the ProtoRev9 version of the CPLD.
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"""
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# ProtoRev9 CFG configuration register bit offsets
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CFG_OSK = 20
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@ -427,10 +489,9 @@ class ProtoRev9(CPLDVersionManager):
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@kernel
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def init(self, cpld):
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"""Initialize and detect Urukul.
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"""Initialize Urukul with ProtoRev9.
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Resets the DDS I/O interface and verifies correct CPLD gateware
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version.
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Resets the DDS I/O interface.
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Does not pulse the DDS ``MASTER_RESET`` as that confuses the AD9910.
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"""
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cfg = cpld.cfg_reg
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@ -451,7 +512,7 @@ class ProtoRev9(CPLDVersionManager):
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@kernel
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def set_profile(self, cpld, channel: TInt32, profile: TInt32):
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"""Set the CFG.PROFILE[0:2] pins for a channel.
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"""Set the CFG.PROFILE[0:2] pins for the given channel.
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:param profile: PROFILE pins in numeric representation (0-7).
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:param channel: Channel (0-3).
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@ -477,86 +538,18 @@ class ProtoRev9(CPLDVersionManager):
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@kernel
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def _configure_all_bits(self, cpld, bit_offset: TInt32, state: TInt32):
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"""Configure all four bits of a specific type in the configuration register.
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"""Configure all four bits at a specific bit offset in the configuration register.
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:param bit_offset: Base bit offset for the configuration type
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:param bit_offset: bit offset for the configuration bits
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:param state: State as a 4-bit integer
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"""
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cpld.cfg_write(
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(cpld.cfg_reg & ~(int64(0xF) << bit_offset)) | (int64(state) << bit_offset)
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)
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@kernel
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def cfg_att_en(self, cpld, channel: TInt32, on: TBool):
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"""Configure the ATT_EN bit through the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_ATT_EN, channel, on)
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@kernel
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def cfg_att_en_all(self, cpld, state: TInt32):
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"""Configure all four ATT_EN bits through the configuration register.
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:param state: OSK state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_ATT_EN, state)
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@kernel
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def cfg_osk(self, cpld, channel: TInt32, on: TBool):
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"""Configure the OSK bit through the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_OSK, channel, on)
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@kernel
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def cfg_osk_all(self, cpld, state: TInt32):
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"""Configure all four OSK bits through the configuration register.
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:param state: OSK state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_OSK, state)
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@kernel
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def cfg_drctl(self, cpld, channel: TInt32, on: TBool):
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"""Configure the DRCTL bit through the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_DRCTL, channel, on)
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@kernel
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def cfg_drctl_all(self, cpld, state: TInt32):
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"""Configure all four DRCTL bits through the configuration register.
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:param state: DRCTL state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_DRCTL, state)
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@kernel
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def cfg_drhold(self, cpld, channel: TInt32, on: TBool):
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"""Configure the DRHOLD bit through the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_DRHOLD, channel, on)
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@kernel
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def cfg_drhold_all(self, cpld, state: TInt32):
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"""Configure all four DRHOLD bits through the configuration register.
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:param state: DRHOLD state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_DRHOLD, state)
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@kernel
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def cfg_mask_nu(self, cpld, channel: TInt32, on: TBool):
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"""Configure the MASK_NU bits through the configuration register.
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"""Configure the MASK_NU bit for the given channel in the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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@ -565,14 +558,89 @@ class ProtoRev9(CPLDVersionManager):
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@kernel
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def cfg_mask_nu_all(self, cpld, state: TInt32):
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"""Configure all four MASK_NU bits through the configuration register.
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"""Configure all four MASK_NU bits in the configuration register.
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:param state: MASK_NU state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_MASK_NU, state)
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@kernel
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def cfg_att_en(self, cpld, channel: TInt32, on: TBool):
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"""Configure the ATT_EN bit for the given channel in the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_ATT_EN, channel, on)
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@kernel
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def cfg_att_en_all(self, cpld, state: TInt32):
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"""Configure all four ATT_EN bits in the configuration register.
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:param state: OSK state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_ATT_EN, state)
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@kernel
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def cfg_osk(self, cpld, channel: TInt32, on: TBool):
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"""Configure the OSK bit for the given channel in the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_OSK, channel, on)
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@kernel
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def cfg_osk_all(self, cpld, state: TInt32):
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"""Configure all four OSK bits in the configuration register.
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:param state: OSK state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_OSK, state)
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@kernel
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def cfg_drctl(self, cpld, channel: TInt32, on: TBool):
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"""Configure the DRCTL bit for the given channel in the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_DRCTL, channel, on)
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@kernel
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def cfg_drctl_all(self, cpld, state: TInt32):
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"""Configure all four DRCTL bits in the configuration register.
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:param state: DRCTL state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_DRCTL, state)
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@kernel
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def cfg_drhold(self, cpld, channel: TInt32, on: TBool):
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"""Configure the DRHOLD bit for the given channel in the configuration register.
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:param channel: Channel index (0-3)
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:param on: Switch value
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"""
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cpld._configure_bit(ProtoRev9.CFG_DRHOLD, channel, on)
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@kernel
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def cfg_drhold_all(self, cpld, state: TInt32):
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"""Configure all four DRHOLD bits in the configuration register.
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:param state: DRHOLD state as a 4-bit integer.
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"""
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cpld._configure_all_bits(ProtoRev9.CFG_DRHOLD, state)
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class CPLDVersionManagerFactory:
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"""
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Factory class for creating CPLD version managers.
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This class provides a method to instantiate the appropriate `CPLDVersionManager` subclass
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based on the CPLD protocol revision.
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"""
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@staticmethod
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def get_version(proto_rev: int) -> CPLDVersionManager:
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if proto_rev == STA_PROTO_REV_8:
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@ -615,6 +683,7 @@ class CPLD:
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:param sync_div: ``SYNC_IN`` generator divider. The ratio between the coarse
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RTIO frequency and the ``SYNC_IN`` generator frequency (default: 2 if
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`sync_device` was specified).
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:param proto_rev: CPLD protocol revision
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:param core_device: Core device name
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If the clocking is incorrect (for example, setting ``clk_sel`` to the
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@ -730,6 +799,14 @@ class CPLD:
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def _configure_all_bits(self, bit_offset: TInt32, state: TInt32):
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self.version_manager._configure_all_bits(self, bit_offset, state)
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@kernel
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def cfg_mask_nu(self, channel: TInt32, on: TBool):
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self.version_manager.cfg_mask_nu(self, channel, on)
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@kernel
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def cfg_mask_nu_all(self, state: TInt32):
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self.version_manager.cfg_mask_nu_all(self, state)
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@kernel
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def cfg_att_en(self, channel: TInt32, on: TBool):
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self.version_manager.cfg_att_en(self, channel, on)
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@ -762,14 +839,6 @@ class CPLD:
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def cfg_drhold_all(self, state: TInt32):
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self.version_manager.cfg_drhold_all(self, state)
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@kernel
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def cfg_mask_nu(self, channel: TInt32, on: TBool):
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self.version_manager.cfg_mask_nu(self, channel, on)
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@kernel
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def cfg_mask_nu_all(self, state: TInt32):
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self.version_manager.cfg_mask_nu_all(self, state)
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@kernel
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def cfg_sw(self, channel: TInt32, on: TBool):
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"""Configure the RF switches through the configuration register.
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