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jesd204_tools: get the Vivado timing analyzer to behave

This commit is contained in:
Sebastien Bourdeauducq 2019-01-03 20:22:35 +08:00
parent d6a3172a3e
commit 10ebf63c47
1 changed files with 1 additions and 0 deletions
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artiq/gateware/jesd204_tools.py
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@ -37,6 +37,7 @@ class UltrascaleCRG(Module, AutoCSR):
] ]
if use_rtio_clock: if use_rtio_clock:
self.cd_jesd.clk.attr.add("keep")
self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio")) self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio"))
else: else:
self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk) self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk)