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fastino: make driver filter order configurable

This commit is contained in:
Robert Jördens 2021-10-27 20:24:58 +00:00
parent 3f6bf33298
commit 10c37b87ec
1 changed files with 9 additions and 9 deletions
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18
artiq/coredevice/fastino.py
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@ -39,13 +39,15 @@ class Fastino:
:param core_device: Core device name (default: "core") :param core_device: Core device name (default: "core")
:param log2_width: Width of DAC channel group (logarithm base 2). :param log2_width: Width of DAC channel group (logarithm base 2).
Value must match the corresponding value in the RTIO PHY (gateware). Value must match the corresponding value in the RTIO PHY (gateware).
:param order: CIC filter interpolation order.
""" """
kernel_invariants = {"core", "channel", "width"} kernel_invariants = {"core", "channel", "width", "order"}
def __init__(self, dmgr, channel, core_device="core", log2_width=0): def __init__(self, dmgr, channel, core_device="core", log2_width=0, order=3):
self.channel = channel << 8 self.channel = channel << 8
self.core = dmgr.get(core_device) self.core = dmgr.get(core_device)
self.width = 1 << log2_width self.width = 1 << log2_width
self.order = order
@kernel @kernel
def init(self): def init(self):
@ -222,8 +224,7 @@ class Fastino:
Returns the actual interpolation rate. Returns the actual interpolation rate.
The actual overall interpolation gain including gain compensation is The actual overall interpolation gain including gain compensation is
`actual_rate**order/2**ceil(log2(actual_rate**order))` `actual_rate**order/2**ceil(log2(actual_rate**order))`.
where `order = 3`.
""" """
if rate <= 0 or rate > 1 << 16: if rate <= 0 or rate > 1 << 16:
raise ValueError("rate out of bounds") raise ValueError("rate out of bounds")
@ -232,15 +233,14 @@ class Fastino:
while rate_mantissa > 1 << 6: while rate_mantissa > 1 << 6:
rate_exponent += 1 rate_exponent += 1
rate_mantissa >>= 1 rate_mantissa >>= 1
order = 3
gain = 1 gain = 1
for i in range(order): for i in range(self.order):
gain *= rate_mantissa gain *= rate_mantissa
gain_exponent = 0 gain_exponent = 0
while gain > 1 << gain_exponent: while gain > 1 << gain_exponent:
gain_exponent += 1 gain_exponent += 1
gain_exponent += order*rate_exponent gain_exponent += self.order*rate_exponent
assert gain_exponent <= order*16 assert gain_exponent <= self.order*16
self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent) self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
return rate_mantissa << rate_exponent return rate_mantissa << rate_exponent
@ -252,6 +252,6 @@ class Fastino:
continous DAC updates enabled (see :meth:`set_continuous`). continous DAC updates enabled (see :meth:`set_continuous`).
This resets and settles the interpolators. There will be no output This resets and settles the interpolators. There will be no output
updates for the next `order = 3` input samples. updates for the next `order` input samples.
""" """
self.write(0x27, channel_mask) self.write(0x27, channel_mask)