mirror of https://github.com/m-labs/artiq.git
suservo: fix restart timing
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parent
c304b6207a
commit
105068ad90
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@ -26,7 +26,7 @@ class Servo(Module):
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self.start = Signal()
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self.start = Signal()
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t_restart = t_cycle - t_adc
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t_restart = t_cycle - t_adc
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assert t_restart > 0
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assert t_restart > 0
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cnt = Signal(max=t_restart)
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cnt = Signal(max=t_restart + 1)
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cnt_done = Signal()
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cnt_done = Signal()
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token = Signal(2)
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token = Signal(2)
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self.done = Signal()
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self.done = Signal()
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@ -44,7 +44,7 @@ class Servo(Module):
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cnt.eq(cnt - 1),
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cnt.eq(cnt - 1),
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),
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),
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If(self.adc.start,
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If(self.adc.start,
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cnt.eq(t_restart - 1),
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cnt.eq(t_restart),
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),
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),
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If(self.adc.done,
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If(self.adc.done,
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token[0].eq(0)
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token[0].eq(0)
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