diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 31e5b4865..b06eef461 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -192,17 +192,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) - self.config["DDS_CHANNEL_COUNT"] = 8 - self.config["DDS_AD9858"] = True - dds_pins = platform.request("dds") - self.comb += dds_pins.p.eq(0) - phy = dds.AD9858(dds_pins, 8) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=512, - ififo_depth=4)) - spi_pins = Module() spi_pins.cs_n = pmod.d[0] spi_pins.mosi = pmod.d[1] @@ -214,6 +203,17 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=32, ififo_depth=32)) + self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) + self.config["DDS_CHANNEL_COUNT"] = 8 + self.config["DDS_AD9858"] = True + dds_pins = platform.request("dds") + self.comb += dds_pins.p.eq(0) + phy = dds.AD9858(dds_pins, 8) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, + ofifo_depth=512, + ififo_depth=4)) + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index ec372418e..8a947dab6 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -153,5 +153,5 @@ Interface Type 2 (SPI) and 2A (expanded SPI): +--------------+--------+--------+--------+--------+ | RTIO channel | CS_N | MOSI | MISO | CLK | +==============+========+========+========+========+ -| 28 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | +| 27 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | +--------------+--------+--------+--------+--------+