From 100bda2582eb939ae08bb395144e1e2f655016ce Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 31 Dec 2017 12:10:16 +0800 Subject: [PATCH] artiq_flash: ignore RTM FPGA It has no flash connected, and attempting to detect it causes unnecessary program failure when the RTM is not present. --- artiq/frontend/artiq_flash.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/artiq/frontend/artiq_flash.py b/artiq/frontend/artiq_flash.py index eebbd9b8d..5f9f2f0db 100755 --- a/artiq/frontend/artiq_flash.py +++ b/artiq/frontend/artiq_flash.py @@ -147,9 +147,8 @@ class ProgrammerSayma(Programmer): "adapter_khz 5000", "transport select jtag", - "source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0 "set CHIP XCKU040", - "source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1 + "source [find cpld/xilinx-xcu.cfg]", "target create xcu.proxy testee -chain-position xcu.tap", "set XILINX_USER1 0x02", @@ -159,11 +158,11 @@ class ProgrammerSayma(Programmer): ] self.init() - def load(self, bitfile, pld=1): - self.prog.append("pld load {} {{{}}}".format(pld, bitfile)) + def load(self, bitfile): + self.prog.append("pld load 0 {{{}}}".format(bitfile)) - def proxy(self, proxy_bitfile, pld=1): - self.load(proxy_bitfile, pld) + def proxy(self, proxy_bitfile): + self.load(proxy_bitfile) self.prog.append("reset halt") def flash_binary(self, flashno, address, filename):