M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 19:28:26 +08:00
Code Issues Projects Releases Wiki Activity

spi: fix typo in doc

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2017-07-20 22:18:21 +08:00
parent 4e9165fd1d
commit 0ffc752310
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/coredevice/spi.py
View File

@ -74,7 +74,7 @@ class SPIMaster:
def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz): def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
"""Set the configuration register. """Set the configuration register.
* If ``config.cs_polarity`` == 0 (```cs`` active low, the default), * If ``config.cs_polarity`` == 0 (``cs`` active low, the default),
"``cs_n`` all deasserted" means "all ``cs_n`` bits high". "``cs_n`` all deasserted" means "all ``cs_n`` bits high".
* ``cs_n`` is not mandatory in the pads supplied to the gateware core. * ``cs_n`` is not mandatory in the pads supplied to the gateware core.
Framing and chip selection can also be handled independently Framing and chip selection can also be handled independently