From 0fe0f4d433ad2f89c2c97060621da16fdc1962eb Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 27 Aug 2015 11:09:33 +0800 Subject: [PATCH] dds: fix phase computation. Closes #79. --- artiq/coredevice/dds.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py index 037df881c..e9e830331 100644 --- a/artiq/coredevice/dds.py +++ b/artiq/coredevice/dds.py @@ -131,11 +131,11 @@ class _DDSGeneric: """ if phase_mode == _PHASE_MODE_DEFAULT: phase_mode = self.phase_mode - syscall("dds_set", now_mu(), self.channel, - frequency, round(phase*2**self.pow_width), phase_mode) + syscall("dds_set", now_mu(), self.channel, frequency, + phase, phase_mode) @kernel - def set(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT): + def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT): """Like ``set_mu``, but uses Hz and turns.""" self.set_mu(self.frequency_to_ftw(frequency), self.turns_to_pow(phase), phase_mode)