mirror of https://github.com/m-labs/artiq.git
artiq_compile: actually disable attribute writeback.
I wrote both halves of this condition but forgot to hook them together. Fixes #586.
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@ -40,7 +40,8 @@ class Source:
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return cls(source.Buffer(f.read(), filename, 1), engine=engine)
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class Module:
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def __init__(self, src, ref_period=1e-6):
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def __init__(self, src, ref_period=1e-6, attribute_writeback=True):
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self.attribute_writeback = attribute_writeback
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self.engine = src.engine
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self.embedding_map = src.embedding_map
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self.name = src.name
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@ -79,7 +80,8 @@ class Module:
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llvm_ir_generator = transforms.LLVMIRGenerator(
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engine=self.engine, module_name=self.name, target=target,
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embedding_map=self.embedding_map)
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return llvm_ir_generator.process(self.artiq_ir, attribute_writeback=True)
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return llvm_ir_generator.process(self.artiq_ir,
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attribute_writeback=self.attribute_writeback)
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def __repr__(self):
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printer = types.TypePrinter()
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@ -81,7 +81,7 @@ class Core:
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self.core = self
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self.comm.core = self
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def compile(self, function, args, kwargs, set_result=None, with_attr_writeback=True):
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def compile(self, function, args, kwargs, set_result=None, attribute_writeback=True):
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try:
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engine = _DiagnosticEngine(all_errors_are_fatal=True)
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@ -89,7 +89,9 @@ class Core:
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stitcher.stitch_call(function, args, kwargs, set_result)
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stitcher.finalize()
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module = Module(stitcher, ref_period=self.ref_period)
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module = Module(stitcher,
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ref_period=self.ref_period,
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attribute_writeback=attribute_writeback)
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target = OR1KTarget()
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library = target.compile_and_link([module])
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@ -55,7 +55,7 @@ def main():
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object_map, kernel_library, _, _ = \
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core.compile(exp.run, [exp_inst], {},
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with_attr_writeback=False)
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attribute_writeback=False)
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except CompileError as error:
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return
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finally:
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