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hmc7043: fix SYSREF to meet s/h at FPGA (#794)

This commit is contained in:
Sebastien Bourdeauducq 2018-06-18 17:04:12 +08:00
parent 6272052d15
commit 0e640a6d6f
1 changed files with 1 additions and 1 deletions
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artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -172,7 +172,7 @@ pub mod hmc7043 {
(false, 0, 0x0, 0x0, 0x08), // 4: ADC2_CLK (false, 0, 0x0, 0x0, 0x08), // 4: ADC2_CLK
(false, 0, 0x0, 0x0, 0x08), // 5: ADC2_SYSREF (false, 0, 0x0, 0x0, 0x08), // 5: ADC2_SYSREF
(false, 0, 0x0, 0x0, 0x08), // 6: GTP_CLK2 (false, 0, 0x0, 0x0, 0x08), // 6: GTP_CLK2
(true, SYSREF_DIV, 0x0, 0x0, 0x10), // 7: FPGA_DAC_SYSREF, LVDS (true, SYSREF_DIV, 0x0, 0x2, 0x10), // 7: FPGA_DAC_SYSREF, LVDS
(true, FPGA_CLK_DIV, 0x0, 0x0, 0x08), // 8: GTP_CLK1 (true, FPGA_CLK_DIV, 0x0, 0x0, 0x08), // 8: GTP_CLK1
(false, 0, 0x0, 0x0, 0x10), // 9: AMC_MASTER_AUX_CLK (false, 0, 0x0, 0x0, 0x10), // 9: AMC_MASTER_AUX_CLK
(false, 0, 0x0, 0x0, 0x10), // 10: RTM_MASTER_AUX_CLK (false, 0, 0x0, 0x0, 0x10), // 10: RTM_MASTER_AUX_CLK