mirror of https://github.com/m-labs/artiq.git
targets/kc705/qc2: hook up HPC backplane
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parent
cb8e497ff6
commit
0e1f75ec49
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@ -1,66 +1,66 @@
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import itertools
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from migen.build.generic_platform import *
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fmc_adapter_io = [
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("ttl", 0, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA02_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA09_P"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
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("ttl", 16, Pins("LPC:LA13_N"), IOStandard("LVTTL")),
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("ttl", 17, Pins("LPC:LA14_N"), IOStandard("LVTTL")),
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("ttl", 18, Pins("LPC:LA17_CC_P"), IOStandard("LVTTL")),
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("ttl", 19, Pins("LPC:LA17_CC_N"), IOStandard("LVTTL")),
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("ttl", 20, Pins("LPC:LA18_CC_P"), IOStandard("LVTTL")),
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("ttl", 21, Pins("LPC:LA18_CC_N"), IOStandard("LVTTL")),
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("ttl", 22, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 23, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 24, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 25, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 26, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 27, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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__all__ = ["fmc_adapter_io"]
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("dds", 0,
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Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "
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"LPC:LA20_N LPC:LA19_P LPC:LA20_P")),
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Subsignal("d", Pins("LPC:LA15_N LPC:LA16_N LPC:LA15_P LPC:LA16_P "
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"LPC:LA11_N LPC:LA12_N LPC:LA11_P LPC:LA12_P "
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"LPC:LA07_N LPC:LA08_N LPC:LA07_P LPC:LA08_P "
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"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
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Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
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"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
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"LPC:LA30_N LPC:LA33_P LPC:LA33_N LPC:LA32_P")),
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Subsignal("fud", Pins("LPC:LA21_N")),
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Subsignal("wr_n", Pins("LPC:LA24_P")),
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Subsignal("rd_n", Pins("LPC:LA25_N")),
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Subsignal("rst", Pins("LPC:LA25_P")),
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ttl_pins = [
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"LA00_CC_P", "LA02_P", "LA00_CC_N", "LA02_N", "LA01_CC_P", "LA01_CC_N", "LA06_P", "LA06_N",
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"LA05_P", "LA05_N", "LA10_P", "LA09_P", "LA10_N", "LA09_N", "LA13_P", "LA14_P", "LA13_N",
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"LA14_N", "LA17_CC_P", "LA17_CC_N", "LA18_CC_P", "LA18_CC_N", "LA23_P", "LA23_N", "LA27_P",
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"LA26_P", "LA27_N", "LA26_N"
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]
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def get_fmc_adapter_io():
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ttl = itertools.count()
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dds = itertools.count()
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i2c_fmc = itertools.count()
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clk_m2c = itertools.count()
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r = []
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for connector in "LPC", "HPC":
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for ttl_pin in ttl_pins:
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r.append(("ttl", next(ttl),
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Pins(connector + ":" + ttl_pin), IOStandard("LVTTL")))
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def FPins(s):
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return Pins(s.replace("FMC:", connector + ":"))
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r += [
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("dds", next(dds),
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Subsignal("a", FPins("FMC:LA22_N FMC:LA21_P FMC:LA22_P FMC:LA19_N "
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"FMC:LA20_N FMC:LA19_P FMC:LA20_P")),
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Subsignal("d", FPins("FMC:LA15_N FMC:LA16_N FMC:LA15_P FMC:LA16_P "
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"FMC:LA11_N FMC:LA12_N FMC:LA11_P FMC:LA12_P "
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"FMC:LA07_N FMC:LA08_N FMC:LA07_P FMC:LA08_P "
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"FMC:LA04_N FMC:LA03_N FMC:LA04_P FMC:LA03_P")),
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Subsignal("sel_n", FPins("FMC:LA24_N FMC:LA29_P FMC:LA28_P FMC:LA29_N "
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"FMC:LA28_N FMC:LA31_P FMC:LA30_P FMC:LA31_N "
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"FMC:LA30_N FMC:LA33_P FMC:LA33_N FMC:LA32_P")),
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Subsignal("fud", FPins("FMC:LA21_N")),
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Subsignal("wr_n", FPins("FMC:LA24_P")),
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Subsignal("rd_n", FPins("FMC:LA25_N")),
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Subsignal("rst", FPins("FMC:LA25_P")),
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IOStandard("LVTTL")),
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("i2c_fmc", 0,
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Subsignal("scl", Pins("LPC:IIC_SCL")),
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Subsignal("sda", Pins("LPC:IIC_SDA")),
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("i2c_fmc", next(i2c_fmc),
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Subsignal("scl", FPins("FMC:IIC_SCL")),
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Subsignal("sda", FPins("FMC:IIC_SDA")),
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IOStandard("LVCMOS25")),
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("clk_m2c", 0,
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Subsignal("p", Pins("LPC:CLK0_M2C_P")),
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Subsignal("n", Pins("LPC:CLK0_M2C_N")),
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("clk_m2c", next(clk_m2c),
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Subsignal("p", FPins("FMC:CLK0_M2C_P")),
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Subsignal("n", FPins("FMC:CLK0_M2C_N")),
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IOStandard("LVDS")),
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("clk_m2c", 1,
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Subsignal("p", Pins("LPC:CLK1_M2C_P")),
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Subsignal("n", Pins("LPC:CLK1_M2C_N")),
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("clk_m2c", next(clk_m2c),
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Subsignal("p", FPins("FMC:CLK1_M2C_P")),
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Subsignal("n", FPins("FMC:CLK1_M2C_N")),
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IOStandard("LVDS")),
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]
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return r
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fmc_adapter_io = get_fmc_adapter_io()
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@ -300,7 +300,7 @@ class NIST_CLOCK(_NIST_Ions):
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class NIST_QC2(_NIST_Ions):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 12 DDS channels. Current implementation for single backplane.
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and 24 DDS channels.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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@ -309,16 +309,25 @@ class NIST_QC2(_NIST_Ions):
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platform.add_extension(nist_qc2.fmc_adapter_io)
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rtio_channels = []
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clock_generators = []
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for backplane_offset in 0, 28:
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# TTL0-23 are In+Out capable
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for i in range(24):
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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phy = ttl_serdes_7series.Inout_8X(
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platform.request("ttl", backplane_offset+i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# TTL24-26 are output only
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for i in range(24, 27):
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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phy = ttl_serdes_7series.Output_8X(
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platform.request("ttl", backplane_offset+i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# TTL27 is for the clock generator
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phy = ttl_simple.ClockGen(
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platform.request("ttl", backplane_offset+27))
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self.submodules += phy
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clock_generators.append(rtio.Channel.from_phy(phy))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
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self.submodules += phy
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@ -328,17 +337,17 @@ class NIST_QC2(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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# TTL27 is for the clock generator
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phy = ttl_simple.ClockGen(platform.request("ttl", 27))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# add clock generators after RTIO_REGULAR_TTL_COUNT
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rtio_channels += clock_generators
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["RTIO_DDS_COUNT"] = 2
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self.config["DDS_CHANNELS_PER_BUS"] = 12
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self.config["DDS_AD9914"] = True
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self.config["DDS_ONEHOT_SEL"] = True
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phy = dds.AD9914(platform.request("dds"), 12, onehot=True)
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for backplane_offset in range(2):
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phy = dds.AD9914(
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platform.request("dds", backplane_offset), 12, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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