mirror of https://github.com/m-labs/artiq.git
pipistrello: make pmod extension header, cleanup
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parent
a8fe3f50c3
commit
0d431cb019
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@ -9,11 +9,10 @@ from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import wishbone
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from misoc.cores import gpio
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from misoc.integration.soc_core import mem_decoder
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from misoc.targets.pipistrello import (BaseSoC, soc_pipistrello_args,
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soc_pipistrello_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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@ -24,6 +23,28 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
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from artiq import __version__ as artiq_version
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_pmod_spi = [
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("pmod_spi", 0,
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Subsignal("cs_n", Pins("PMOD:0")),
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Subsignal("mosi", Pins("PMOD:1")),
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Subsignal("miso", Pins("PMOD:2")),
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Subsignal("clk", Pins("PMOD:3")),
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IOStandard("LVTTL")
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),
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("pmod_extended_spi", 0,
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Subsignal("cs_n", Pins("PMOD:0")),
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Subsignal("mosi", Pins("PMOD:1")),
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Subsignal("miso", Pins("PMOD:2")),
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Subsignal("clk", Pins("PMOD:3")),
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Subsignal("int", Pins("PMOD:4")),
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Subsignal("rst", Pins("PMOD:5")),
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Subsignal("d0", Pins("PMOD:6")),
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Subsignal("d1", Pins("PMOD:7")),
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IOStandard("LVTTL")
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),
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]
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, clk_freq):
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self._clock_sel = CSRStorage()
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@ -88,7 +109,8 @@ class _RTIOCRG(Module, AutoCSR):
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# ISE infers correct period constraints for cd_rtio.clk from
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# the internal clock. The first two TIGs target just the BUFGMUX.
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platform.add_platform_command("""
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platform.add_platform_command(
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"""
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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NET "{ext_clk}" TNM_NET = "GRPext_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
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@ -97,8 +119,9 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
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NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
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TIMESPEC "TSfix_ise3" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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""", ext_clk=rtio_external_clk, int_clk=rtio_internal_clk,
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rtio_clk=self.cd_rtio.clk)
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""",
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ext_clk=rtio_external_clk, int_clk=rtio_internal_clk,
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rtio_clk=self.cd_rtio.clk)
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class NIST_QC1(BaseSoC, AMPSoC):
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@ -112,9 +135,9 @@ class NIST_QC1(BaseSoC, AMPSoC):
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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@ -134,6 +157,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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"""
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platform.add_extension(nist_qc1.papilio_adapter_io)
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platform.add_extension(_pmod_spi)
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4))
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@ -177,13 +201,14 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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pmod = self.platform.request("pmod", 0)
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spi_pins = self.platform.request("pmod_extended_spi", 0)
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for i in range(4, 8):
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phy = ttl_simple.Inout(pmod.d[i])
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for i, p in enumerate((spi_pins.int, spi_pins.rst,
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spi_pins.d0, spi_pins.d1)):
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phy = ttl_simple.Inout(p)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
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ofifo_depth=128))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
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ofifo_depth=4))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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@ -191,16 +216,11 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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spi_pins = Module()
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spi_pins.cs_n = pmod.d[0]
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spi_pins.mosi = pmod.d[1]
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spi_pins.miso = pmod.d[2]
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spi_pins.clk = pmod.d[3]
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phy = spi.SPIMaster(spi_pins)
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy, ofifo_depth=64, ififo_depth=64))
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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@ -222,8 +242,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
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self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
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self.get_native_sdram_if())
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.get_native_sdram_if())
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def main():
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