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rtio: add FIFO level CSR
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parent
3b4bb41a19
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0cb18d58a8
@ -6,13 +6,14 @@ from migen.genlib.cdc import MultiReg
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class RTIOChannelO(Module):
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def __init__(self, signal, counter_width, fifo_depth):
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self.submodules.fifo = SyncFIFOBuffered([
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("timestamp", counter_width), ("level", 1)],
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("timestamp", counter_width), ("value", 1)],
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fifo_depth)
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self.event = self.fifo.din
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self.writable = self.fifo.writable
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self.we = self.fifo.we
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self.underflow = Signal()
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self.level = self.fifo.level
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###
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@ -31,17 +32,18 @@ class RTIOChannelO(Module):
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(self.fifo.dout.timestamp == counter)),
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self.fifo.re.eq(time_hit)
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]
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self.sync += If(time_hit, signal.eq(self.fifo.dout.level))
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self.sync += If(time_hit, signal.eq(self.fifo.dout.value))
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class RTIO(Module, AutoCSR):
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def __init__(self, channels, counter_width=32, ofifo_depth=8, ififo_depth=8):
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(bits_for(len(channels)-1))
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self._r_o_timestamp = CSRStorage(counter_width)
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self._r_o_level = CSRStorage()
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self._r_o_value = CSRStorage()
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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channel_os = []
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for n, channel in enumerate(channels):
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@ -51,12 +53,13 @@ class RTIO(Module, AutoCSR):
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self.comb += [
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channel_o.reset.eq(self._r_reset.storage),
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channel_o.event.timestamp.eq(self._r_o_timestamp.storage),
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channel_o.event.level.eq(self._r_o_level.storage),
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channel_o.event.value.eq(self._r_o_value.storage),
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channel_o.we.eq(self._r_o_we.re & (self._r_chan_sel == n))
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]
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channel_o = Array(channel_os)[self._r_chan_sel.storage]
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self.comb += [
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self._r_o_writable.status.eq(channel_o.writable),
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self._r_o_underflow.status.eq(channel_o.underflow)
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self._r_o_underflow.status.eq(channel_o.underflow),
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self._r_o_level.status.eq(channel_o.level)
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]
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