mirror of https://github.com/m-labs/artiq.git
Merge branch 'master' of https://github.com/m-labs/artiq
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commit
0b10f72c2b
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@ -14,39 +14,40 @@ class _AD9xxx(Module):
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# # #
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# # #
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# buffer the current address/data on the rtlink output
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current_address = Signal.like(self.rtlink.o.address)
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current_data = Signal.like(self.rtlink.o.data)
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self.sync.rio += If(self.rtlink.o.stb,
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current_address.eq(self.rtlink.o.address),
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current_data.eq(self.rtlink.o.data))
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# keep track of the currently selected channel
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# keep track of the currently selected channel
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current_channel = Signal(max=nchannels)
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current_channel = Signal(max=nchannels)
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self.sync.rio += If(self.rtlink.o.stb &
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self.sync.rio += If(current_address == 2**flen(pads.a) + 1,
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(self.rtlink.o.address == 2**flen(pads.a)+1),
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current_channel.eq(current_data))
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current_channel.eq(self.rtlink.o.data))
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# keep track of frequency tuning words, before they are FUDed
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# keep track of frequency tuning words, before they are FUDed
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ftws = [Signal(32) for i in range(nchannels)]
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ftws = [Signal(32) for i in range(nchannels)]
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for c, ftw in enumerate(ftws):
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for c, ftw in enumerate(ftws):
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if flen(pads.d) == 8:
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if flen(pads.d) == 8:
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for i in range(4):
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self.sync.rio += \
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self.sync.rio += \
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If(current_channel == c, [
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If(self.rtlink.o.stb & \
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If(current_address == ftw_base+i,
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(self.rtlink.o.address == ftw_base+i) & \
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ftw[i*8:(i+1)*8].eq(current_data))
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(current_channel == c),
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for i in range(4)])
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ftw[i*8:(i+1)*8].eq(self.rtlink.o.data)
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)
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elif flen(pads.d) == 16:
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elif flen(pads.d) == 16:
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for i in range(2):
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self.sync.rio += \
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self.sync.rio += \
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If(current_channel == c, [
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If(self.rtlink.o.stb & \
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If(current_address == ftw_base+2*i,
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(self.rtlink.o.address == ftw_base+2*i) & \
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ftw[i*16:(i+1)*16].eq(current_data))
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(current_channel == c),
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for i in range(2)])
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ftw[i*16:(i+1)*16].eq(self.rtlink.o.data)
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)
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else:
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else:
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raise NotImplementedError
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raise NotImplementedError
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# FTW to probe on FUD
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# FTW to probe on FUD
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for c, (probe, ftw) in enumerate(zip(self.probes, ftws)):
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self.sync.rio += If(current_address == 2**flen(pads.a), [
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fud = self.rtlink.o.stb & \
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If(current_channel == c, probe.eq(ftw))
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(self.rtlink.o.address == 2**flen(pads.a))
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for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
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self.sync.rio += If(fud & (current_channel == c), probe.eq(ftw))
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class AD9858(_AD9xxx):
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class AD9858(_AD9xxx):
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