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Merge branch 'master' of https://github.com/m-labs/artiq

This commit is contained in:
Sebastien Bourdeauducq 2015-07-22 10:44:49 +08:00
parent 073e09ed36 47191eda91
commit 0b10f72c2b
1 changed files with 22 additions and 21 deletions
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39
artiq/gateware/rtio/phy/dds.py
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@ -14,39 +14,40 @@ class _AD9xxx(Module):
# # # # # #
# buffer the current address/data on the rtlink output
current_address = Signal.like(self.rtlink.o.address)
current_data = Signal.like(self.rtlink.o.data)
self.sync.rio += If(self.rtlink.o.stb,
current_address.eq(self.rtlink.o.address),
current_data.eq(self.rtlink.o.data))
# keep track of the currently selected channel # keep track of the currently selected channel
current_channel = Signal(max=nchannels) current_channel = Signal(max=nchannels)
self.sync.rio += If(self.rtlink.o.stb & self.sync.rio += If(current_address == 2**flen(pads.a) + 1,
(self.rtlink.o.address == 2**flen(pads.a)+1), current_channel.eq(current_data))
current_channel.eq(self.rtlink.o.data))
# keep track of frequency tuning words, before they are FUDed # keep track of frequency tuning words, before they are FUDed
ftws = [Signal(32) for i in range(nchannels)] ftws = [Signal(32) for i in range(nchannels)]
for c, ftw in enumerate(ftws): for c, ftw in enumerate(ftws):
if flen(pads.d) == 8: if flen(pads.d) == 8:
for i in range(4):
self.sync.rio += \ self.sync.rio += \
If(self.rtlink.o.stb & \ If(current_channel == c, [
(self.rtlink.o.address == ftw_base+i) & \ If(current_address == ftw_base+i,
(current_channel == c), ftw[i*8:(i+1)*8].eq(current_data))
ftw[i*8:(i+1)*8].eq(self.rtlink.o.data) for i in range(4)])
)
elif flen(pads.d) == 16: elif flen(pads.d) == 16:
for i in range(2):
self.sync.rio += \ self.sync.rio += \
If(self.rtlink.o.stb & \ If(current_channel == c, [
(self.rtlink.o.address == ftw_base+2*i) & \ If(current_address == ftw_base+2*i,
(current_channel == c), ftw[i*16:(i+1)*16].eq(current_data))
ftw[i*16:(i+1)*16].eq(self.rtlink.o.data) for i in range(2)])
)
else: else:
raise NotImplementedError raise NotImplementedError
# FTW to probe on FUD # FTW to probe on FUD
for c, (probe, ftw) in enumerate(zip(self.probes, ftws)): self.sync.rio += If(current_address == 2**flen(pads.a), [
fud = self.rtlink.o.stb & \ If(current_channel == c, probe.eq(ftw))
(self.rtlink.o.address == 2**flen(pads.a)) for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
self.sync.rio += If(fud & (current_channel == c), probe.eq(ftw))
class AD9858(_AD9xxx): class AD9858(_AD9xxx):