diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
index b54cc7f8d..c02c4a40b 100644
--- a/soc/targets/artiq_pipistrello.py
+++ b/soc/targets/artiq_pipistrello.py
@@ -4,6 +4,7 @@ from migen.bank import wbgen
 from mibuild.generic_platform import *
 
 from misoclib.com import gpio
+from misoclib.soc import mem_decoder
 from targets.pipistrello import BaseSoC
 
 from artiq.gateware import rtio, ad9858
@@ -124,12 +125,12 @@ class ARTIQMidiSoC(BaseSoC):
 
         rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
-        self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
+        self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
         self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
 
         dds_pads = platform.request("dds")
         self.submodules.dds = ad9858.AD9858(dds_pads)
-        self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
+        self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
         self.comb += dds_pads.fud_n.eq(~fud)