drtio: reset aux packet gateware after locking to recovered clock

Closes #949

artiq/firmware/libdrtioaux/lib.rs

@@ -269,6 +269,17 @@ pub mod hw {
     use super::*;
     use std::io::Cursor;
 
+    pub fn reset(linkno: u8) {
+        let linkno = linkno as usize;
+        unsafe {
+            // clear buffer first to limit race window with buffer overflow
+            // error. We assume the CPU is fast enough so that no two packets
+            // will be received between the buffer and the error flag are cleared.
+            (board::csr::DRTIO[linkno].aux_rx_present_write)(1);
+            (board::csr::DRTIO[linkno].aux_rx_error_write)(1);
+        }
+    }
+
     fn rx_has_error(linkno: u8) -> bool {
         let linkno = linkno as usize;
         unsafe {

artiq/firmware/satman/main.rs

@@ -237,6 +237,7 @@ fn startup() {
         info!("link is up, switching to recovered clock");
         si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
         si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
+        drtioaux::hw::reset(0);
         drtio_reset(false);
         drtio_reset_phy(false);
         while drtio_link_rx_up() {