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docs: fix snippet to advance the timeline by one coarse RTIO cycle 

Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
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Etienne Wodey 2021-06-22 11:48:06 +02:00 committed by Sébastien Bourdeauducq
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commit 094a346974
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doc/manual/rtio.rst
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@ -131,7 +131,7 @@ Notes:
* Configuring the gateware with more lanes for the RTIO core reduces the frequency of sequence errors.
* The number of lanes is a hard limit on the number of simultaneous RTIO output events.
* Whether a particular sequence of timestamps causes a sequence error or not is fully deterministic (starting from a known RTIO state, e.g. after a reset). Adding a constant offset to the whole sequence does not affect the result.
* Zero-duration methods (such as :meth:`artiq.coredevice.ttl.TTLOut.on()`) do not advance the timeline and so will consume additional lanes if they are scheduled simultaneously. Adding a tiny delay will prevent this (e.g. ``delay_mu(self.core.ref_multiplier)``, at least one coarse rtio cycle).
* Zero-duration methods (such as :meth:`artiq.coredevice.ttl.TTLOut.on()`) do not advance the timeline and so will consume additional lanes if they are scheduled simultaneously. Adding a tiny delay will prevent this (e.g. ``delay_mu(np.int64(self.core.ref_multiplier))``, at least one coarse rtio cycle).
The offending event is discarded and the RTIO core keeps operating.