From 0824e0aeaedbebd6a266d1e92a0cb7bad9af76b0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 16 Sep 2017 17:04:11 +0800 Subject: [PATCH] gateware/targets: remove deprecated ofifo_depth parameter --- artiq/gateware/targets/kc705_dds.py | 22 +++++++++------------- artiq/gateware/targets/kc705_sma_spi.py | 4 ++-- artiq/gateware/targets/phaser.py | 3 +-- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index 7aad8930b..6c56fea26 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -224,24 +224,22 @@ class NIST_CLOCK(_NIST_Ions): phy = spi.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) + phy, ififo_depth=4)) for i in range(3): phy = spi.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=128, ififo_depth=128)) - + phy, ififo_depth=128)) + phy = spi.SPIMaster(platform.request("sdcard_spi_33", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) - + phy, ififo_depth=4)) + phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=512, - ififo_depth=4)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) @@ -299,21 +297,19 @@ class NIST_QC2(_NIST_Ions): phy = spi.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) + phy, ififo_depth=4)) for i in range(4): phy = spi.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=128, ififo_depth=128)) + phy, ififo_depth=128)) for backplane_offset in range(2): phy = dds.AD9914( platform.request("dds", backplane_offset), 12, onehot=True) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=512, - ififo_depth=4)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) diff --git a/artiq/gateware/targets/kc705_sma_spi.py b/artiq/gateware/targets/kc705_sma_spi.py index cea74c574..63f91a3a5 100755 --- a/artiq/gateware/targets/kc705_sma_spi.py +++ b/artiq/gateware/targets/kc705_sma_spi.py @@ -101,12 +101,12 @@ class SMA_SPI(_NIST_Ions): phy = spi.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) + phy, ififo_depth=4)) phy = spi.SPIMaster(self.platform.request("sma_spi")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=128, ififo_depth=128)) + phy, ififo_depth=128)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index fe141837f..ba63b3819 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -213,8 +213,7 @@ class Phaser(MiniSoC, AMPSoC): sysref_pads = platform.request("ad9154_sysref") phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, - ofifo_depth=2)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32)) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend(rtio.Channel.from_phy(phy)