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rtio: do not reset DDS and SPI PHYs on RTIO reset (#503)

This commit is contained in:
Sebastien Bourdeauducq 2016-07-09 10:07:19 +08:00 committed by Robert Jordens
parent eceafad7e3
commit 078a9abeb9
2 changed files with 2 additions and 2 deletions
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2
artiq/gateware/rtio/phy/dds.py
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@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
class _AD9xxx(Module):
def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio")(
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
ad9xxx.AD9xxx(pads, **kwargs))
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
self.rtlink = self._rt2wb.rtlink

2
artiq/gateware/rtio/phy/spi.py
View File

@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
class SPIMaster(Module):
def __init__(self, pads, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio")(
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
SPIMasterWB(pads, **kwargs))
self.submodules._rt2wb = RT2WB(2, self._ll.bus)
self.rtlink = self._rt2wb.rtlink