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mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00

aqctl_coreanalyzer_proxy: cleanup

This commit is contained in:
Sebastien Bourdeauducq 2023-12-08 18:56:10 +08:00
parent b09a39c82e
commit 05a9422e67

View File

@ -2,13 +2,14 @@ import argparse
import asyncio
import atexit
import logging
import struct
from sipyco.asyncio_tools import AsyncioServer, SignalHandler, atexit_register_coroutine
from sipyco.pc_rpc import Server
from sipyco import common_args
from artiq.coredevice.comm_analyzer import get_analyzer_dump
logger = logging.getLogger(__name__)
@ -38,9 +39,8 @@ class ProxyServer(AsyncioServer):
writer.close()
def request_dump_cb(self, dump):
encoded_dump = struct.pack(">L", len(dump)) + dump
for recipient in self._recipients:
recipient.put_nowait(encoded_dump)
recipient.put_nowait(dump)
class ProxyControl:
@ -99,8 +99,6 @@ def main():
loop.run_until_complete(server.start(bind_address, args.port_control))
atexit_register_coroutine(server.stop, loop=loop)
logger.info("ARTIQ core analyzer proxy is ready.")
_, pending = loop.run_until_complete(asyncio.wait(
[loop.create_task(signal_handler.wait_terminate()),
loop.create_task(server.wait_terminate())],