mirror of https://github.com/m-labs/artiq.git
pdq2: driver and unittest
* parses wavesynth style programs * verified with cosimulated gateware
This commit is contained in:
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200e20fb39
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05781699b8
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@ -1,38 +1,45 @@
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# Robert Jordens <jordens@gmail.com>, 2012-2015
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# Robert Jordens <jordens@gmail.com>, 2012-2015
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from math import log2, sqrt
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import logging
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import logging
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import struct
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import struct
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import warnings
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import numpy as np
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from scipy import interpolate
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import serial
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import serial
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logger = logging.getLogger(__name__)
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logger = logging.getLogger(__name__)
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class Segment:
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class Segment:
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max_time = 1 << 16 # uint16 timer
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max_val = 1 << 15 # int16 DAC
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max_out = 10. # Volt
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out_scale = max_val/max_out
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cordic_gain = 1.
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for i in range(16):
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cordic_gain *= sqrt(1 + 2**(-2*i))
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def __init__(self):
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def __init__(self):
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self.data = b""
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self.data = b""
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def line(self, typ, dt, data, trigger=False, silence=False,
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def line(self, typ, duration, data, trigger=False, silence=False,
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aux=False, shift=0, end=False, clear=False, wait=False):
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aux=False, shift=0, jump=False, clear=False, wait_trigger=False):
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assert len(data) % 2 == 0, data
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assert len(data) % 2 == 0, data
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assert len(data)//2 <= 14
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assert len(data)//2 <= 14
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#assert dt*(1 << shift) > 1 + len(data)//2
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#assert dt*(1 << shift) > 1 + len(data)//2
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head = (
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header = (
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1 + len(data)//2 | (typ << 4) | (trigger << 6) | (silence << 7) |
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1 + len(data)//2 | (typ << 4) | (trigger << 6) | (silence << 7) |
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(aux << 8) | (shift << 9) | (end << 13) | (clear << 14) |
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(aux << 8) | (shift << 9) | (jump << 13) | (clear << 14) |
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(wait << 15)
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(wait_trigger << 15)
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)
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)
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self.data += struct.pack("<HH", head, dt) + data
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self.data += struct.pack("<HH", header, duration) + data
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@staticmethod
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@staticmethod
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def pack(widths, values):
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def pack(widths, values):
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fmt = "<"
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fmt = "<"
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ud = []
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ud = []
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for width, value in zip(widths, values):
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for width, value in zip(widths, values):
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if width == 3:
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value = int(round(value * (1 << 16*width)))
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if width == 2:
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ud.append(value & 0xffff)
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ud.append(value & 0xffff)
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fmt += "H"
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fmt += "H"
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value >>= 16
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value >>= 16
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@ -42,96 +49,40 @@ class Segment:
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try:
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try:
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return struct.pack(fmt, *ud)
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return struct.pack(fmt, *ud)
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except struct.error as e:
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except struct.error as e:
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logger.error("%s as %s: %s", ud, fmt, e)
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logger.error("can not pack %s as %s (%s as %s): %s",
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values, widths, ud, fmt, e)
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raise e
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raise e
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def lines(self, typ, dt, widths, v, first={}, mid={}, last={}, shift=0):
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n = len(dt) - 1
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dt = dt.astype(np.uint16)
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v = v.astype(np.int64)
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for i, (dti, vi) in enumerate(zip(dt, v)):
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opts = mid
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if i == 0:
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opts = first
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elif i == n:
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opts = last
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data = self.pack(widths, vi)
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self.line(typ, dti, data, shift=shift, **opts)
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@staticmethod
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@staticmethod
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def interpolate(t, v, order, t_eval, widths=None):
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def compensate(coef):
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"""Spline interpolating derivatives for t,v.
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"""compensates higher order spline coefficients for integrator chain
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The returned spline coefficients are one shorter than t
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latency"""
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"""
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order = len(coef)
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if order == 0:
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return np.rint(v[:, None])
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# FIXME: does not ensure that interpolates do not clip
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s = interpolate.splrep(t, v, k=order)
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# FIXME: needs k knots outside t_eval
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# dv = np.array(interpolate.spalde(t_eval, s))
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dv = np.array([interpolate.splev(t_eval, s, der=i, ext=0)
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for i in range(order + 1)]).T
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# correct for adder chain latency
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if order > 1:
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dv[:, 1] += dv[:, 2]/2
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if order > 2:
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if order > 2:
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dv[:, 1] += dv[:, 3]/6
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coef[1] += coef[2]/2.
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dv[:, 2] += dv[:, 3]
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if order > 3:
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if widths is not None:
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coef[1] += coef[3]/6.
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dv *= 1 << 16*widths
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coef[2] += coef[3]
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return np.rint(dv)
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return coef
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def line_times(self, t, tr=None):
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def bias(self, amplitude=[], **kwargs):
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if tr is None:
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coef = self.compensate([self.out_scale*a for a in amplitude])
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tr = np.rint(t)
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data = self.pack([0, 1, 2, 2], coef)
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if len(tr) == 1:
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self.line(typ=0, data=data, **kwargs)
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return None, np.array([1])
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dt = np.diff(tr)
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assert np.all(dt >= 0)
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assert np.all(dt < (1 << 16))
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return tr[:-1], dt
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def dac(self, t, v, first={}, mid={}, last={},
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def dds(self, amplitude=[], phase=[], **kwargs):
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shift=0, tr=None, order=3, stop=True):
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scale = self.out_scale/self.cordic_gain
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widths = np.array([1, 2, 3, 3])
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coef = self.compensate([scale*a for a in amplitude])
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tr, dt = self.line_times(t, tr)
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if phase:
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dv = self.interpolate(t, v, order, tr, widths[:order + 1] - 1)
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assert len(amplitude) == 4
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self.lines(0, dt, widths, dv, first, mid, mid if stop else last, shift)
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coef += [p*self.max_val for p in phase]
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if stop:
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data = self.pack([0, 1, 2, 2, 0, 1, 1], coef)
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self.line(0, 2, self.pack([1], [int(round(v[-1]))]), **last)
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self.line(typ=1, data=data, **kwargs)
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def dds(self, t, v, p=None, f=None, first={}, mid={}, last={},
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shift=0, tr=None, order=3, stop=True):
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widths = np.array([1, 2, 3, 3, 1, 2, 2])
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tr, dt = self.line_times(t, tr)
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dv = self.interpolate(t, v, order, tr, widths[:order + 1] - 1)
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if p is not None:
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assert order == 3
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dp = self.interpolate(t, p, 1, tr)[:, :1]
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dv = np.concatenate((dv, dp), axis=1)
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if f is not None:
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df = self.interpolate(t, f, 1, tr, widths[-2:] - 1)
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dv = np.concatenate((dv, df), axis=1)
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self.lines(1, dt, widths, dv, first, mid, mid if stop else last, shift)
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if stop:
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dv = [int(round(v[-1])), 0, 0, 0]
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if p is not None:
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dv.append(int(round(p[-1])))
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if f is not None:
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dv.append(int(round(f[-1])))
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self.line(1, 2, self.pack(widths, dv), **last)
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class Channel:
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class Channel:
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max_data = 4*(1 << 10) # 8kx16 8kx16 4kx16
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num_frames = 8
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num_frames = 8
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max_val = 1 << 15 # int16 bit DAC
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max_data = 4*(1 << 10) # 8kx16 8kx16 4kx16
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max_time = 1 << 16 # uint16 bit timer
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cordic_gain = 1.
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for i in range(16):
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cordic_gain *= np.sqrt(1 + 2**(-2*i))
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max_out = 10.
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freq = 50e6 # samples/s
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def __init__(self):
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def __init__(self):
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self.segments = []
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self.segments = []
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@ -145,29 +96,6 @@ class Channel:
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self.segments.append(segment)
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self.segments.append(segment)
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return segment
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return segment
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def segment(self, t, v, p=None, f=None,
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order=3, aux=False, shift=0, trigger=True, end=True,
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silence=False, stop=True, clear=True, wait=False):
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segment = self.new_segment()
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t = t*(self.freq/2**shift)
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v = np.clip(v/self.max_out, -1, 1)
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order = min(order, len(t) - 1)
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first = dict(trigger=trigger, clear=clear, aux=aux)
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mid = dict(aux=aux)
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last = dict(silence=silence, end=end, wait=wait, aux=aux)
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if p is None:
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v = v*self.max_val
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segment.dac(t, v, first, mid, last, shift=shift, order=order,
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stop=stop)
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else:
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v = v*(self.max_val/self.cordic_gain)
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p = p*(self.max_val/np.pi)
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if f is not None:
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f = f*(self.max_val/self.freq)
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segment.dds(t, v, p, f, first, mid, last, shift=shift,
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order=order, stop=stop)
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return segment
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def place(self):
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def place(self):
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addr = self.num_frames
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addr = self.num_frames
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for segment in self.segments:
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for segment in self.segments:
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@ -196,27 +124,26 @@ class Pdq2:
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PDQ DAC (a.k.a. QC_Waveform)
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PDQ DAC (a.k.a. QC_Waveform)
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"""
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"""
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num_dacs = 3
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num_dacs = 3
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num_boards = 3
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num_channels = num_dacs*num_boards
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_escape = b"\xa5"
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_escape = b"\xa5"
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_commands = "RESET TRIGGER ARM DCM START".split()
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_commands = "RESET TRIGGER ARM DCM START".split()
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def __init__(self, url=None, dev=None):
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def __init__(self, url=None, dev=None, num_boards=3):
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if dev is None:
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if dev is None:
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dev = serial.serial_for_url(url)
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dev = serial.serial_for_url(url)
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self.dev = dev
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self.dev = dev
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self.num_boards = num_boards
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self.num_channels = self.num_dacs * self.num_boards
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self.channels = [Channel() for i in range(self.num_channels)]
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self.channels = [Channel() for i in range(self.num_channels)]
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self.set_freq()
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def set_freq(self, f=50e6):
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for c in self.channels:
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c.freq = f
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def close(self):
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def close(self):
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self.dev.close()
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self.dev.close()
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del self.dev
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del self.dev
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def clear_all(self):
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for channel in self.channels:
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channel.clear()
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def write(self, data):
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def write(self, data):
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logger.debug("> %r", data)
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logger.debug("> %r", data)
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written = self.dev.write(data)
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written = self.dev.write(data)
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@ -236,29 +163,41 @@ class Pdq2:
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data = data.replace(self._escape, self._escape + self._escape)
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data = data.replace(self._escape, self._escape + self._escape)
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self.write(data)
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self.write(data)
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def write_channel(self, channel, entry=None):
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def write_channel(self, channel):
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self.write_mem(self.channels.index(channel),
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self.write_mem(self.channels.index(channel),
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channel.serialize(entry))
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channel.serialize())
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def write_all(self):
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def write_all(self):
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for channel in self.channels:
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for channel in self.channels:
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self.write_mem(self.channels.index(channel),
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self.write_mem(self.channels.index(channel),
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channel.serialize())
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channel.serialize())
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def write_table(self, channel, segments=None):
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def write_table(self, channel):
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# no segment placement
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# no segment placement
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# no segment writing
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# no segment writing
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self.write_mem(channel, self.channels[channel].table(segments))
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self.write_mem(channel, self.channels[channel].table())
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def write_segment(self, channel, segment):
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def write_segment(self, channel, segment):
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# no collision check
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# no collision check
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s = self.channels[channel].segments[segment]
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s = self.channels[channel].segments[segment]
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self.write_mem(channel, s.data, s.adr)
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self.write_mem(channel, s.data, s.adr)
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def multi_segment(self, times_voltages, channel, map=None, **kwargs):
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def program(self, program):
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warnings.warn("deprecated", DeprecationWarning)
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self.clear_all()
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c = self.channels[channel]
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for segment_data in program:
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del c.segments[:]
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segments = [c.new_segment() for c in self.channels]
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for t, v in times_voltages:
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for line in segment_data:
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c.segment(t, v, **kwargs)
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dac_divider = line.get("dac_divider", 1)
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return c.serialize(map)
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shift = int(log2(dac_divider))
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assert 2**shift == dac_divider
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duration = line["duration"]
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jump = line.get("jump", False)
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wait_trigger = line.get("wait_trigger", False)
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for segment, data in zip(segments, line.get("channel_data")):
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assert len(data) == 1
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for target, target_data in data.items():
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getattr(segment, target)(
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shift=shift, duration=duration,
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wait_trigger=wait_trigger, jump=jump,
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**target_data)
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self.write_all()
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@ -0,0 +1,92 @@
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import unittest
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import os
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import io
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from artiq.devices.pdq2.driver import Pdq2
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no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE")) \
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or bool(os.getenv("ARTIQ_NO_PERIPHERALS"))
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pdq2_source = os.getenv("ARTIQ_PDQ2_SOURCE")
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class TestPdq2(unittest.TestCase):
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def setUp(self):
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self.dev = Pdq2(dev=io.BytesIO())
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def test_reset(self):
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self.dev.cmd("RESET", True)
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buf = self.dev.dev.getvalue()
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self.assertEqual(buf, b"\xa5\x00")
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def test_program(self):
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self.dev.program(_test_program)
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@unittest.skipUnless(pdq2_source, "no pdq2 source and gateware")
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def test_gateware(self):
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self.dev.cmd("START", False)
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self.dev.cmd("ARM", False)
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self.dev.program(_test_program)
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self.dev.cmd("START", True)
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self.dev.cmd("ARM", True)
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#self.dev.cmd("TRIGGER", True)
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buf = self.dev.dev.getvalue()
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import sys
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sys.path.append(pdq2_source)
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from gateware.pdq2 import Pdq2Sim
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from migen.sim.generic import run_simulation
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from matplotlib import pyplot as plt
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import numpy as np
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tb = Pdq2Sim(buf)
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tb.ctrl_pads.trigger.reset = 0
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run_simulation(tb, vcd_name="pdq2.vcd", ncycles=700)
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out = np.array(tb.outputs, np.uint16).view(np.int16)
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for outi in out[len(buf):].T:
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plt.step(np.arange(len(outi)), outi)
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plt.show()
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_test_program = [
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[
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{
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"duration": 20,
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"channel_data": [
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{"bias": {"amplitude": [0, 0, 2e-3]}},
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{"bias": {"amplitude": [1, 0, -7.5e-3, 7.5e-4]}},
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{"dds": {
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"amplitude": [0, 0, 4e-3, 0],
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||||||
|
"phase": [.5, .05],
|
||||||
|
}},
|
||||||
|
],
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"duration": 40,
|
||||||
|
"channel_data": [
|
||||||
|
{"bias": {"amplitude": [.4, .04, -2e-3]}},
|
||||||
|
{"bias": {
|
||||||
|
"amplitude": [.5],
|
||||||
|
"silence": True,
|
||||||
|
}},
|
||||||
|
{"dds": {
|
||||||
|
"amplitude": [.8, .08, -4e-3, 0],
|
||||||
|
"phase": [.5, .05, .04/40],
|
||||||
|
"clear": True,
|
||||||
|
}},
|
||||||
|
],
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"duration": 20,
|
||||||
|
"channel_data": [
|
||||||
|
{"bias": {"amplitude": [.4, -.04, 2e-3]}},
|
||||||
|
{"bias": {"amplitude": [.5, 0, -7.5e-3, 7.5e-4]}},
|
||||||
|
{"dds": {
|
||||||
|
"amplitude": [.8, -.08, 4e-3, 0],
|
||||||
|
"phase": [-.5],
|
||||||
|
}},
|
||||||
|
],
|
||||||
|
"wait_trigger": True,
|
||||||
|
"jump": True,
|
||||||
|
},
|
||||||
|
]
|
||||||
|
]
|
Loading…
Reference in New Issue