rtio: disable replace on rt2wb channels

artiq/gateware/rtio/core.py

@@ -129,24 +129,28 @@ class _OutputManager(Module):
         collision = Signal()
         any_error = Signal()
         nop = Signal()
-        self.sync.rsys += [
+        if interface.enable_replace:
             # Note: replace may be asserted at the same time as collision
             # when addresses are different. In that case, it is a collision.
-            replace.eq(self.ev.timestamp == buf.timestamp),
+            self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
+        self.sync.rsys += \
             # Detect sequence errors on coarse timestamps only
             # so that they are mutually exclusive with collision errors.
             sequence_error.eq(self.ev.timestamp[fine_ts_width:]
                               < buf.timestamp[fine_ts_width:])
-        ]
-        if hasattr(self.ev, "a"):
-            different_addresses = self.ev.a != buf.a
+        if interface.enable_replace:
+            if hasattr(self.ev, "a"):
+                different_addresses = self.ev.a != buf.a
+            else:
+                different_addresses = 0
+            if fine_ts_width:
+                self.sync.rsys += collision.eq(
+                    (self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
+                    & ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
+                       |different_addresses))
         else:
-            different_addresses = 0
-        if fine_ts_width:
             self.sync.rsys += collision.eq(
-                (self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
-                & ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
-                   |different_addresses))
+                self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
         self.comb += any_error.eq(sequence_error | collision)
         if interface.suppress_nop:
             # disable NOP at reset: do not suppress a first write with all 0s

artiq/gateware/rtio/phy/wishbone.py

@@ -13,7 +13,8 @@ class RT2WB(Module):
             rtlink.OInterface(
                 len(wb.dat_w),
                 address_width + 1,
-                suppress_nop=False),
+                suppress_nop=False,
+                enable_replace=False),
             rtlink.IInterface(
                 len(wb.dat_r),
                 timestamped=False)

artiq/gateware/rtio/rtlink.py

@@ -3,7 +3,8 @@ from migen import *
 
 class OInterface:
     def __init__(self, data_width, address_width=0,
-                 fine_ts_width=0, suppress_nop=True):
+                 fine_ts_width=0, suppress_nop=True,
+                 enable_replace=True):
         self.stb = Signal()
         self.busy = Signal()
 
@@ -15,6 +16,7 @@ class OInterface:
             self.fine_ts = Signal(fine_ts_width)
 
         self.suppress_nop = suppress_nop
+        self.enable_replace = enable_replace
 
     @classmethod
     def like(cls, other):