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rtio: disable replace on rt2wb channels

This commit is contained in:
Sebastien Bourdeauducq 2016-03-09 23:37:04 +08:00
parent 1c706fae49
commit 03b53c3af9
3 changed files with 19 additions and 12 deletions
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24
artiq/gateware/rtio/core.py
View File

@ -129,24 +129,28 @@ class _OutputManager(Module):
collision = Signal() collision = Signal()
any_error = Signal() any_error = Signal()
nop = Signal() nop = Signal()
self.sync.rsys += [ if interface.enable_replace:
# Note: replace may be asserted at the same time as collision # Note: replace may be asserted at the same time as collision
# when addresses are different. In that case, it is a collision. # when addresses are different. In that case, it is a collision.
replace.eq(self.ev.timestamp == buf.timestamp), self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
self.sync.rsys += \
# Detect sequence errors on coarse timestamps only # Detect sequence errors on coarse timestamps only
# so that they are mutually exclusive with collision errors. # so that they are mutually exclusive with collision errors.
sequence_error.eq(self.ev.timestamp[fine_ts_width:] sequence_error.eq(self.ev.timestamp[fine_ts_width:]
< buf.timestamp[fine_ts_width:]) < buf.timestamp[fine_ts_width:])
] if interface.enable_replace:
if hasattr(self.ev, "a"): if hasattr(self.ev, "a"):
different_addresses = self.ev.a != buf.a different_addresses = self.ev.a != buf.a
else:
different_addresses = 0
if fine_ts_width:
self.sync.rsys += collision.eq(
(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
|different_addresses))
else: else:
different_addresses = 0
if fine_ts_width:
self.sync.rsys += collision.eq( self.sync.rsys += collision.eq(
(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:]) self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
|different_addresses))
self.comb += any_error.eq(sequence_error | collision) self.comb += any_error.eq(sequence_error | collision)
if interface.suppress_nop: if interface.suppress_nop:
# disable NOP at reset: do not suppress a first write with all 0s # disable NOP at reset: do not suppress a first write with all 0s

3
artiq/gateware/rtio/phy/wishbone.py
View File

@ -13,7 +13,8 @@ class RT2WB(Module):
rtlink.OInterface( rtlink.OInterface(
len(wb.dat_w), len(wb.dat_w),
address_width + 1, address_width + 1,
suppress_nop=False), suppress_nop=False,
enable_replace=False),
rtlink.IInterface( rtlink.IInterface(
len(wb.dat_r), len(wb.dat_r),
timestamped=False) timestamped=False)

4
artiq/gateware/rtio/rtlink.py
View File

@ -3,7 +3,8 @@ from migen import *
class OInterface: class OInterface:
def __init__(self, data_width, address_width=0, def __init__(self, data_width, address_width=0,
fine_ts_width=0, suppress_nop=True): fine_ts_width=0, suppress_nop=True,
enable_replace=True):
self.stb = Signal() self.stb = Signal()
self.busy = Signal() self.busy = Signal()
@ -15,6 +16,7 @@ class OInterface:
self.fine_ts = Signal(fine_ts_width) self.fine_ts = Signal(fine_ts_width)
self.suppress_nop = suppress_nop self.suppress_nop = suppress_nop
self.enable_replace = enable_replace
@classmethod @classmethod
def like(cls, other): def like(cls, other):