mirror of https://github.com/m-labs/artiq.git
rtio: disable replace on rt2wb channels
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parent
1c706fae49
commit
03b53c3af9
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@ -129,15 +129,16 @@ class _OutputManager(Module):
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collision = Signal()
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collision = Signal()
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any_error = Signal()
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any_error = Signal()
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nop = Signal()
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nop = Signal()
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self.sync.rsys += [
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if interface.enable_replace:
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# Note: replace may be asserted at the same time as collision
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# Note: replace may be asserted at the same time as collision
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# when addresses are different. In that case, it is a collision.
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# when addresses are different. In that case, it is a collision.
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replace.eq(self.ev.timestamp == buf.timestamp),
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self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
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self.sync.rsys += \
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# Detect sequence errors on coarse timestamps only
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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# so that they are mutually exclusive with collision errors.
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sequence_error.eq(self.ev.timestamp[fine_ts_width:]
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sequence_error.eq(self.ev.timestamp[fine_ts_width:]
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< buf.timestamp[fine_ts_width:])
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< buf.timestamp[fine_ts_width:])
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]
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if interface.enable_replace:
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if hasattr(self.ev, "a"):
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if hasattr(self.ev, "a"):
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different_addresses = self.ev.a != buf.a
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different_addresses = self.ev.a != buf.a
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else:
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else:
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@ -147,6 +148,9 @@ class _OutputManager(Module):
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(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
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& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
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|different_addresses))
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|different_addresses))
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else:
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self.sync.rsys += collision.eq(
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self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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self.comb += any_error.eq(sequence_error | collision)
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self.comb += any_error.eq(sequence_error | collision)
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if interface.suppress_nop:
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if interface.suppress_nop:
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# disable NOP at reset: do not suppress a first write with all 0s
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# disable NOP at reset: do not suppress a first write with all 0s
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@ -13,7 +13,8 @@ class RT2WB(Module):
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rtlink.OInterface(
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rtlink.OInterface(
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len(wb.dat_w),
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len(wb.dat_w),
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address_width + 1,
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address_width + 1,
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suppress_nop=False),
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suppress_nop=False,
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enable_replace=False),
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rtlink.IInterface(
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rtlink.IInterface(
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len(wb.dat_r),
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len(wb.dat_r),
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timestamped=False)
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timestamped=False)
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@ -3,7 +3,8 @@ from migen import *
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class OInterface:
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class OInterface:
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def __init__(self, data_width, address_width=0,
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def __init__(self, data_width, address_width=0,
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fine_ts_width=0, suppress_nop=True):
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fine_ts_width=0, suppress_nop=True,
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enable_replace=True):
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self.stb = Signal()
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self.stb = Signal()
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self.busy = Signal()
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self.busy = Signal()
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@ -15,6 +16,7 @@ class OInterface:
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self.fine_ts = Signal(fine_ts_width)
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self.fine_ts = Signal(fine_ts_width)
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self.suppress_nop = suppress_nop
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self.suppress_nop = suppress_nop
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self.enable_replace = enable_replace
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@classmethod
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@classmethod
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def like(cls, other):
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def like(cls, other):
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