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transforms.interleaver: fix IR type/value mismatch.
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@ -102,7 +102,7 @@ class Interleaver:
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assert isinstance(source_terminator, ir.Delay)
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if is_pure_delay(old_decomp):
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new_decomp_expr = ir.Constant(target_time_delta, builtins.TInt64())
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new_decomp_expr = ir.Constant(int(target_time_delta), builtins.TInt64())
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new_decomp = ir.Builtin("delay_mu", [new_decomp_expr], builtins.TNone())
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new_decomp.loc = old_decomp.loc
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source_terminator.basic_block.insert(source_terminator, new_decomp)
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