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artiq
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si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER 

The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
This commit is contained in:
Sebastien Bourdeauducq 2018-02-17 13:54:50 +08:00
parent cfb21ca126
commit 039dee4c8e
3 changed files with 7 additions and 7 deletions
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8
artiq/firmware/runtime/main.rs
View File

@ -89,8 +89,8 @@ fn startup() {
#[cfg(has_i2c)] #[cfg(has_i2c)]
board_artiq::i2c::init(); board_artiq::i2c::init();
#[cfg(si5324_free_running)] #[cfg(si5324_as_synthesizer)]
setup_si5324_free_running(); setup_si5324_as_synthesizer();
#[cfg(has_hmc830_7043)] #[cfg(has_hmc830_7043)]
board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043"); board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
@ -107,8 +107,8 @@ fn startup() {
} }
} }
#[cfg(si5324_free_running)] #[cfg(si5324_as_synthesizer)]
fn setup_si5324_free_running() fn setup_si5324_as_synthesizer()
{ {
// 125MHz output, from 100MHz CLKIN2 reference, 9 Hz // 125MHz output, from 100MHz CLKIN2 reference, 9 Hz
#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref))] #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref))]

4
artiq/gateware/targets/kasli.py
View File

@ -229,7 +229,7 @@ class Opticlock(_StandaloneBase):
def __init__(self, **kwargs): def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs) _StandaloneBase.__init__(self, **kwargs)
self.config["SI5324_FREE_RUNNING"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_EXT_REF"] = None self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0" self.config["RTIO_FREQUENCY"] = "125.0"
@ -323,7 +323,7 @@ class Master(MiniSoC, AMPSoC):
self.config["I2C_BUS_COUNT"] = 1 self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_FREE_RUNNING"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.comb += platform.request("sfp_ctl", 2).tx_disable.eq(0) self.comb += platform.request("sfp_ctl", 2).tx_disable.eq(0)

2
artiq/gateware/targets/sayma_amc.py
View File

@ -292,7 +292,7 @@ class Master(MiniSoC, AMPSoC):
self.csr_devices.append("i2c") self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1 self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_FREE_RUNNING"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.transceiver = gth_ultrascale.GTH( self.submodules.transceiver = gth_ultrascale.GTH(