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coreanalyzer: use VCD scopes for DDS/SPI

This commit is contained in:
Robert Jördens 2017-02-18 14:25:01 +01:00
parent 7519408857
commit 039ced6637
1 changed files with 19 additions and 10 deletions
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29
artiq/coredevice/analyzer.py
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@ -1,6 +1,7 @@
from operator import itemgetter from operator import itemgetter
from collections import namedtuple from collections import namedtuple
from itertools import count from itertools import count
from contextlib import contextmanager
import struct import struct
import logging import logging
@ -118,6 +119,12 @@ class VCDManager:
.format(name=name, code=code, width=width)) .format(name=name, code=code, width=width))
return VCDChannel(self.out, code) return VCDChannel(self.out, code)
@contextmanager
def scope(self, name):
self.out.write("$scope module {} $end\n".format(name))
yield
self.out.write("$upscope $end\n")
def set_time(self, time): def set_time(self, time):
if time != self.current_time: if time != self.current_time:
self.out.write("#{}\n".format(time)) self.out.write("#{}\n".format(time))
@ -178,10 +185,11 @@ class DDSHandler:
def add_dds_channel(self, name, dds_channel_nr): def add_dds_channel(self, name, dds_channel_nr):
dds_channel = dict() dds_channel = dict()
dds_channel["vcd_frequency"] = \ with self.vcd_manager.scope("dds/{}".format(name)):
self.vcd_manager.get_channel("dds/" + name + "/frequency", 64) dds_channel["vcd_frequency"] = \
dds_channel["vcd_phase"] = \ self.vcd_manager.get_channel(name + "/frequency", 64)
self.vcd_manager.get_channel("dds/" + name + "/phase", 64) dds_channel["vcd_phase"] = \
self.vcd_manager.get_channel(name + "/phase", 64)
if self.dds_type == "DDSChannelAD9914": if self.dds_type == "DDSChannelAD9914":
dds_channel["ftw"] = [None, None] dds_channel["ftw"] = [None, None]
dds_channel["pow"] = None dds_channel["pow"] = None
@ -266,12 +274,13 @@ class SPIMasterHandler(WishboneHandlerMixin):
def __init__(self, vcd_manager, name): def __init__(self, vcd_manager, name):
super().__init__(read_bit=0b100) super().__init__(read_bit=0b100)
self.channels = {} self.channels = {}
for reg_name, reg_width in [ with vcd_manager.scope("spi/{}".format(name)):
("config", 32), for reg_name, reg_width in [
("chip_select", 16), ("write_length", 8), ("read_length", 8), ("config", 32), ("chip_select", 16),
("write", 32), ("read", 32)]: ("write_length", 8), ("read_length", 8),
self.channels[reg_name] = vcd_manager.get_channel( ("write", 32), ("read", 32)]:
"/".join((name, reg_name)), reg_width) self.channels[reg_name] = vcd_manager.get_channel(
"{}/{}".format(name, reg_name), reg_width)
def process_write(self, address, data): def process_write(self, address, data):
if address == 0: if address == 0: