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satman: wait for CPLL/QPLL lock after setting drtio_transceiver::stable_clkin

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Sebastien Bourdeauducq 2019-01-07 17:09:19 +08:00
parent 0ec01790fe
commit 0303267d7e
1 changed files with 1 additions and 0 deletions
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artiq/firmware/satman/main.rs
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@ -302,6 +302,7 @@ pub extern fn main() -> i32 {
unsafe {
csr::drtio_transceiver::stable_clkin_write(1);
}
clock::spin_us(1500); // wait for CPLL/QPLL lock
init_rtio_crg();
#[cfg(has_allaki_atts)]