firmware: rename libboard to libboard_misoc.

By analogy with libbuild_misoc. Hopefully one day it actually gets
moved to misoc...

artiq/firmware/Cargo.lock

@@ -8,7 +8,22 @@ version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 
 [[package]]
-name = "board"
+name = "board_artiq"
+version = "0.0.0"
+dependencies = [
+ "bitflags 1.0.1 (registry+https://github.com/rust-lang/crates.io-index)",
+ "board_misoc 0.0.0",
+ "build_artiq 0.0.0",
+ "build_misoc 0.0.0",
+ "byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
+ "crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
+ "io 0.0.0",
+ "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
+ "proto 0.0.0",
+]
+
+[[package]]
+name = "board_misoc"
 version = "0.0.0"
 dependencies = [
  "build_misoc 0.0.0",
@@ -19,26 +34,11 @@ dependencies = [
  "smoltcp 0.4.0 (git+https://github.com/m-labs/smoltcp?rev=181083f)",
 ]
 
-[[package]]
-name = "board_artiq"
-version = "0.0.0"
-dependencies = [
- "bitflags 1.0.1 (registry+https://github.com/rust-lang/crates.io-index)",
- "board 0.0.0",
- "build_artiq 0.0.0",
- "build_misoc 0.0.0",
- "byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "io 0.0.0",
- "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
- "proto 0.0.0",
-]
-
 [[package]]
 name = "bootloader"
 version = "0.0.0"
 dependencies = [
- "board 0.0.0",
+ "board_misoc 0.0.0",
  "build_misoc 0.0.0",
  "byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
  "crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -127,8 +127,8 @@ dependencies = [
 name = "ksupport"
 version = "0.0.0"
 dependencies = [
- "board 0.0.0",
  "board_artiq 0.0.0",
+ "board_misoc 0.0.0",
  "build_misoc 0.0.0",
  "cslice 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "dyld 0.0.0",
@@ -166,7 +166,7 @@ source = "git+https://github.com/whitequark/rust-log_buffer?rev=rust-1.25#ff84e5
 name = "logger_artiq"
 version = "0.0.0"
 dependencies = [
- "board 0.0.0",
+ "board_misoc 0.0.0",
  "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
  "log_buffer 1.2.0 (git+https://github.com/whitequark/rust-log_buffer?rev=rust-1.25)",
 ]
@@ -197,8 +197,8 @@ name = "runtime"
 version = "0.0.0"
 dependencies = [
  "alloc_list 0.0.0",
- "board 0.0.0",
  "board_artiq 0.0.0",
+ "board_misoc 0.0.0",
  "build_artiq 0.0.0",
  "build_misoc 0.0.0",
  "byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -227,8 +227,8 @@ dependencies = [
 name = "satman"
 version = "0.0.0"
 dependencies = [
- "board 0.0.0",
  "board_artiq 0.0.0",
+ "board_misoc 0.0.0",
  "build_artiq 0.0.0",
  "build_misoc 0.0.0",
  "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",

artiq/firmware/bootloader/Cargo.toml

@@ -15,7 +15,7 @@ build_misoc = { path = "../libbuild_misoc" }
 [dependencies]
 byteorder = { version = "1.0", default-features = false }
 crc = { version = "1.7", default-features = false }
-board = { path = "../libboard", features = ["uart_console", "smoltcp"] }
+board_misoc = { path = "../libboard_misoc", features = ["uart_console", "smoltcp"] }
 
 [dependencies.smoltcp]
 git = "https://github.com/m-labs/smoltcp"

artiq/firmware/bootloader/main.rs

@@ -5,15 +5,15 @@ extern crate crc;
 extern crate byteorder;
 extern crate smoltcp;
 #[macro_use]
-extern crate board;
+extern crate board_misoc;
 
 use core::{ptr, slice};
 use crc::crc32;
 use byteorder::{ByteOrder, BigEndian};
-use board::{boot, cache};
+use board_misoc::{ident, cache, sdram, boot, mem as board_mem};
 #[cfg(has_ethmac)]
-use board::{clock, config, ethmac};
+use board_misoc::{clock, config, ethmac};
-use board::uart_console::Console;
+use board_misoc::uart_console::Console;
 
 fn check_integrity() -> bool {
     extern {
@@ -31,7 +31,7 @@ fn check_integrity() -> bool {
 }
 
 fn memory_test(total: &mut usize, wrong: &mut usize) -> bool {
-    const MEMORY: *mut u32 = board::mem::MAIN_RAM_BASE as *mut u32;
+    const MEMORY: *mut u32 = board_mem::MAIN_RAM_BASE as *mut u32;
 
     *total = 0;
     *wrong = 0;
@@ -88,11 +88,11 @@ fn startup() -> bool {
         return false
     }
 
-    println!("Gateware ident {}", board::ident::read(&mut [0; 64]));
+    println!("Gateware ident {}", ident::read(&mut [0; 64]));
 
     println!("Initializing SDRAM...");
 
-    if unsafe { board::sdram::init(Some(&mut Console)) } {
+    if unsafe { sdram::init(Some(&mut Console)) } {
         println!("SDRAM initialized");
     } else {
         println!("SDRAM initialization failed");
@@ -111,8 +111,8 @@ fn startup() -> bool {
 }
 
 fn flash_boot() {
-    const FIRMWARE: *mut u8 = board::mem::FLASH_BOOT_ADDRESS as *mut u8;
+    const FIRMWARE: *mut u8 = board_mem::FLASH_BOOT_ADDRESS as *mut u8;
-    const MAIN_RAM: *mut u8 = board::mem::MAIN_RAM_BASE as *mut u8;
+    const MAIN_RAM: *mut u8 = board_mem::MAIN_RAM_BASE as *mut u8;
 
     println!("Booting from flash...");
 

artiq/firmware/ksupport/Cargo.toml

@@ -16,6 +16,6 @@ build_misoc = { path = "../libbuild_misoc" }
 cslice = { version = "0.3" }
 io = { path = "../libio", features = ["byteorder"] }
 dyld = { path = "../libdyld" }
-board = { path = "../libboard" }
+board_misoc = { path = "../libboard_misoc" }
 board_artiq = { path = "../libboard_artiq" }
 proto = { path = "../libproto" }

artiq/firmware/ksupport/api.rs

@@ -90,8 +90,8 @@ static mut API: &'static [(&'static str, *const ())] = &[
     api!(cache_get = ::cache_get),
     api!(cache_put = ::cache_put),
 
-    api!(mfspr = ::board::spr::mfspr),
+    api!(mfspr = ::board_misoc::spr::mfspr),
-    api!(mtspr = ::board::spr::mtspr),
+    api!(mtspr = ::board_misoc::spr::mtspr),
 
     /* direct syscalls */
     api!(rtio_init = ::rtio::init),

artiq/firmware/ksupport/lib.rs

@@ -9,7 +9,7 @@ extern crate libc;
 
 extern crate io;
 extern crate dyld;
-extern crate board;
+extern crate board_misoc;
 extern crate board_artiq;
 extern crate proto;
 
@@ -17,7 +17,7 @@ use core::{mem, ptr, slice, str};
 use cslice::{CSlice, AsCSlice};
 use io::Cursor;
 use dyld::Library;
-use board::csr;
+use board_misoc::csr;
 use board_artiq::{mailbox, rpc_queue};
 use proto::{kernel_proto, rpc_proto};
 use kernel_proto::*;

artiq/firmware/ksupport/rtio.rs

@@ -3,7 +3,7 @@ mod imp {
     use core::ptr::{read_volatile, write_volatile};
     use cslice::CSlice;
 
-    use board::csr;
+    use board_misoc::csr;
     use ::send;
     use kernel_proto::*;
 

artiq/firmware/libboard_artiq/Cargo.toml

@@ -18,8 +18,8 @@ byteorder = { version = "1.0", default-features = false }
 crc = { version = "1.7", default-features = false }
 log = { version = "0.4", default-features = false }
 io = { path = "../libio", features = ["byteorder"] }
+board_misoc = { path = "../libboard_misoc" }
 proto = { path = "../libproto" }
-board = { path = "../libboard" }
 
 [features]
 uart_console = []

artiq/firmware/libboard_artiq/ad9154.rs

@@ -1,4 +1,4 @@
-use board::{csr, clock};
+use board_misoc::{csr, clock};
 use ad9154_reg;
 use hmc830_7043::hmc7043;
 

artiq/firmware/libboard_artiq/drtioaux.rs

@@ -3,7 +3,7 @@ use crc;
 
 use io::{Cursor, Error as IoError};
 use io::proto::{ProtoRead, ProtoWrite};
-use board;
+use board_misoc::{csr::DRTIO, mem::DRTIO_AUX, clock};
 
 pub use proto::drtioaux_proto::Packet;
 
@@ -47,17 +47,17 @@ pub fn reset(linkno: u8) {
         // clear buffer first to limit race window with buffer overflow
         // error. We assume the CPU is fast enough so that no two packets
         // will be received between the buffer and the error flag are cleared.
-        (board::csr::DRTIO[linkno].aux_rx_present_write)(1);
+        (DRTIO[linkno].aux_rx_present_write)(1);
-        (board::csr::DRTIO[linkno].aux_rx_error_write)(1);
+        (DRTIO[linkno].aux_rx_error_write)(1);
     }
 }
 
 fn has_rx_error(linkno: u8) -> bool {
     let linkno = linkno as usize;
     unsafe {
-        let error = (board::csr::DRTIO[linkno].aux_rx_error_read)() != 0;
+        let error = (DRTIO[linkno].aux_rx_error_read)() != 0;
         if error {
-            (board::csr::DRTIO[linkno].aux_rx_error_write)(1)
+            (DRTIO[linkno].aux_rx_error_write)(1)
         }
         error
     }
@@ -68,12 +68,11 @@ fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>>
 {
     let linkidx = linkno as usize;
     unsafe {
-        if (board::csr::DRTIO[linkidx].aux_rx_present_read)() == 1 {
+        if (DRTIO[linkidx].aux_rx_present_read)() == 1 {
-            let ptr = board::mem::DRTIO_AUX[linkidx].base +
+            let ptr = DRTIO_AUX[linkidx].base + DRTIO_AUX[linkidx].size / 2;
-                      board::mem::DRTIO_AUX[linkidx].size / 2;
+            let len = (DRTIO[linkidx].aux_rx_length_read)();
-            let len = (board::csr::DRTIO[linkidx].aux_rx_length_read)();
             let result = f(slice::from_raw_parts(ptr as *mut u8, len as usize));
-            (board::csr::DRTIO[linkidx].aux_rx_present_write)(1);
+            (DRTIO[linkidx].aux_rx_present_write)(1);
             Ok(Some(result?))
         } else {
             Ok(None)
@@ -107,8 +106,8 @@ pub fn recv_link(linkno: u8) -> Result<Option<Packet>> {
 
 pub fn recv_timeout_link(linkno: u8, timeout_ms: Option<u64>) -> Result<Packet> {
     let timeout_ms = timeout_ms.unwrap_or(10);
-    let limit = board::clock::get_ms() + timeout_ms;
+    let limit = clock::get_ms() + timeout_ms;
-    while board::clock::get_ms() < limit {
+    while clock::get_ms() < limit {
         match recv_link(linkno)? {
             None => (),
             Some(packet) => return Ok(packet),
@@ -122,12 +121,12 @@ fn transmit<F>(linkno: u8, f: F) -> Result<()>
 {
     let linkno = linkno as usize;
     unsafe {
-        while (board::csr::DRTIO[linkno].aux_tx_read)() != 0 {}
+        while (DRTIO[linkno].aux_tx_read)() != 0 {}
-        let ptr = board::mem::DRTIO_AUX[linkno].base;
+        let ptr = DRTIO_AUX[linkno].base;
-        let len = board::mem::DRTIO_AUX[linkno].size / 2;
+        let len = DRTIO_AUX[linkno].size / 2;
         let len = f(slice::from_raw_parts_mut(ptr as *mut u8, len))?;
-        (board::csr::DRTIO[linkno].aux_tx_length_write)(len as u16);
+        (DRTIO[linkno].aux_tx_length_write)(len as u16);
-        (board::csr::DRTIO[linkno].aux_tx_write)(1);
+        (DRTIO[linkno].aux_tx_write)(1);
         Ok(())
     }
 }
@@ -154,7 +153,7 @@ pub fn send_link(linkno: u8, packet: &Packet) -> Result<()> {
 
 // TODO: routing
 fn get_linkno(nodeno: u8) -> Result<u8> {
-    if nodeno == 0 || nodeno as usize > board::csr::DRTIO.len() {
+    if nodeno == 0 || nodeno as usize > DRTIO.len() {
         return Err(Error::NoRoute)
     }
     Ok(nodeno - 1)

artiq/firmware/libboard_artiq/hmc542.rs

@@ -1,4 +1,4 @@
-use board::{csr, clock};
+use board_misoc::{csr, clock};
 
 const PIN_LE:    u32 = 1 << 0;
 const PIN_SIN:   u32 = 1 << 1;

artiq/firmware/libboard_artiq/hmc830_7043.rs

@@ -11,7 +11,7 @@
  */
 
 mod clock_mux {
-    use board::csr;
+    use board_misoc::csr;
 
     const CLK_SRC_EXT_SEL : u8 = 1 << 0;
     const REF_CLK_SRC_SEL : u8 = 1 << 1;
@@ -28,7 +28,7 @@ mod clock_mux {
 }
 
 mod hmc830 {
-    use board::{csr, clock};
+    use board_misoc::{csr, clock};
 
     const HMC830_WRITES: [(u8, u32); 16] = [
         (0x0, 0x20),
@@ -131,7 +131,7 @@ mod hmc830 {
 }
 
 pub mod hmc7043 {
-    use board::csr;
+    use board_misoc::csr;
 
     // To do: check which output channels we actually need
     const DAC_CLK_DIV: u32 = 2;

artiq/firmware/libboard_artiq/i2c.rs

@@ -1,6 +1,6 @@
 #[cfg(has_i2c)]
 mod imp {
-    use board::{csr, clock};
+    use board_misoc::{csr, clock};
 
     fn half_period() { clock::spin_us(100) }
     fn sda_bit(busno: u8) -> u8 { 1 << (2 * busno + 1) }

artiq/firmware/libboard_artiq/lib.rs

@@ -7,8 +7,8 @@ extern crate byteorder;
 extern crate crc;
 #[macro_use]
 extern crate log;
-extern crate board;
 extern crate io;
+extern crate board_misoc;
 extern crate proto;
 
 pub mod pcr;
@@ -16,7 +16,9 @@ pub mod pcr;
 pub mod i2c;
 pub mod spi;
 
+#[cfg(has_kernel_cpu)]
 pub mod mailbox;
+#[cfg(has_kernel_cpu)]
 pub mod rpc_queue;
 
 #[cfg(has_si5324)]

artiq/firmware/libboard_artiq/mailbox.rs

@@ -1,5 +1,5 @@
 use core::ptr::{read_volatile, write_volatile};
-use board::{mem, cache};
+use board_misoc::{mem, cache};
 
 const MAILBOX: *mut usize = mem::MAILBOX_BASE as *mut usize;
 static mut LAST: usize = 0;

artiq/firmware/libboard_artiq/pcr.rs

@@ -1,4 +1,4 @@
-use board::spr::*;
+use board_misoc::spr::*;
 
 bitflags! {
     pub struct Counters: u32 {

artiq/firmware/libboard_artiq/rpc_queue.rs

@@ -1,6 +1,6 @@
 use core::ptr::{read_volatile, write_volatile};
 use core::slice;
-use board::{mem, cache};
+use board_misoc::{mem, cache};
 
 const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 4) as *mut usize;
 const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 8) as *mut usize;

artiq/firmware/libboard_artiq/serwb.rs

@@ -1,5 +1,5 @@
 use core::{cmp, str};
-use board::{csr, clock};
+use board_misoc::{csr, clock};
 
 fn read_rtm_ident(buf: &mut [u8]) -> &str {
     unsafe {

artiq/firmware/libboard_artiq/si5324.rs

@@ -1,7 +1,7 @@
 use core::result;
-use board::clock;
+use board_misoc::clock;
 #[cfg(not(si5324_soft_reset))]
-use board::csr;
+use board_misoc::csr;
 use i2c;
 
 type Result<T> = result::Result<T, &'static str>;
@@ -269,8 +269,7 @@ pub fn select_input(input: Input) -> Result<()> {
 #[cfg(has_siphaser)]
 pub mod siphaser {
     use super::*;
-    use board::csr;
+    use board_misoc::{csr, clock};
-    use board::clock;
 
     pub fn select_recovered_clock(rc: bool) -> Result<()> {
         write(3,   (read(3)? & 0xdf) | (1 << 5))?;  // DHOLD=1

artiq/firmware/libboard_artiq/spi.rs

@@ -1,6 +1,6 @@
 #[cfg(has_converter_spi)]
 mod imp {
-    use board::csr;
+    use board_misoc::csr;
 
     pub fn set_config(busno: u8, flags: u8, length: u8, div: u8, cs: u8) -> Result<(), ()> {
         if busno != 0 {

artiq/firmware/libboard_misoc/Cargo.toml

@@ -1,11 +1,11 @@
 [package]
 authors = ["M-Labs"]
-name = "board"
+name = "board_misoc"
 version = "0.0.0"
 build = "build.rs"
 
 [lib]
-name = "board"
+name = "board_misoc"
 path = "lib.rs"
 
 [build-dependencies]

artiq/firmware/liblogger_artiq/Cargo.toml

@@ -10,4 +10,4 @@ path = "lib.rs"
 [dependencies]
 log = { version = "0.4", default-features = false }
 log_buffer = { version = "1.2", git = "https://github.com/whitequark/rust-log_buffer", rev = "rust-1.25" }
-board = { path = "../libboard" }
+board_misoc = { path = "../libboard_misoc" }

artiq/firmware/liblogger_artiq/lib.rs

@@ -3,13 +3,13 @@
 extern crate log;
 extern crate log_buffer;
 #[macro_use]
-extern crate board;
+extern crate board_misoc;
 
 use core::cell::{Cell, RefCell, RefMut};
 use core::fmt::Write;
 use log::{Log, LevelFilter};
 use log_buffer::LogBuffer;
-use board::clock;
+use board_misoc::clock;
 
 pub struct LogBufferRef<'a> {
     buffer:        RefMut<'a, LogBuffer<&'static mut [u8]>>,

artiq/firmware/runtime/Cargo.toml

@@ -20,8 +20,8 @@ log = { version = "0.4", default-features = false }
 managed = { version = "0.6", default-features = false, features = ["alloc", "map"] }
 unwind_backtrace = { path = "../libunwind_backtrace" }
 io = { path = "../libio", features = ["byteorder", "std_artiq"] }
-board = { path = "../libboard", features = ["uart_console", "smoltcp"] }
 alloc_list = { path = "../liballoc_list" }
+board_misoc = { path = "../libboard_misoc", features = ["uart_console", "smoltcp"] }
 std_artiq = { path = "../libstd_artiq", features = ["alloc", "io_error_alloc"] }
 logger_artiq = { path = "../liblogger_artiq" }
 board_artiq = { path = "../libboard_artiq" }

artiq/firmware/runtime/analyzer.rs

@@ -1,5 +1,5 @@
 use std::io::{self, Write};
-use board::{csr, cache};
+use board_misoc::{csr, cache};
 use sched::{Io, TcpListener, TcpStream};
 use analyzer_proto::*;
 

artiq/firmware/runtime/kernel.rs

@@ -1,5 +1,5 @@
 use core::ptr;
-use board::csr;
+use board_misoc::csr;
 use mailbox;
 use rpc_queue;
 

artiq/firmware/runtime/main.rs

@@ -14,26 +14,25 @@ extern crate alloc_list;
 extern crate unwind_backtrace;
 extern crate io;
 #[macro_use]
+extern crate board_misoc;
+extern crate board_artiq;
+#[macro_use]
 extern crate std_artiq as std;
 extern crate logger_artiq;
-#[macro_use]
-extern crate board;
-extern crate board_artiq;
 extern crate proto;
 
 use core::convert::TryFrom;
 use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
 
-use board::irq;
+use board_misoc::{csr, irq, ident, clock, boot, config};
-use board::config;
 #[cfg(has_ethmac)]
-use board::ethmac;
+use board_misoc::ethmac;
 #[cfg(has_drtio)]
 use board_artiq::drtioaux;
+use board_artiq::{mailbox, rpc_queue};
 use proto::{mgmt_proto, moninj_proto, rpc_proto, session_proto,kernel_proto};
 #[cfg(has_rtio_analyzer)]
 use proto::analyzer_proto;
-use board_artiq::{mailbox, rpc_queue};
 
 #[cfg(has_rtio_core)]
 mod rtio_mgt;
@@ -56,10 +55,10 @@ mod analyzer;
 
 fn startup() {
     irq::set_ie(true);
-    board::clock::init();
+    clock::init();
     info!("ARTIQ runtime starting...");
     info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
-    info!("gateware version {}", board::ident::read(&mut [0; 64]));
+    info!("gateware version {}", ident::read(&mut [0; 64]));
 
     match config::read_str("log_level", |r| r.map(|s| s.parse())) {
         Ok(Ok(log_level_filter)) => {
@@ -85,10 +84,10 @@ fn startup() {
     board_artiq::serwb::wait_init();
 
     #[cfg(has_uart)] {
-        let t = board::clock::get_ms();
+        let t = clock::get_ms();
         info!("press 'e' to erase startup and idle kernels...");
-        while board::clock::get_ms() < t + 1000 {
+        while clock::get_ms() < t + 1000 {
-            if unsafe { board::csr::uart::rxtx_read() == b'e' } {
+            if unsafe { csr::uart::rxtx_read() == b'e' } {
                 config::remove("startup_kernel").unwrap();
                 config::remove("idle_kernel").unwrap();
                 info!("startup and idle kernels erased");
@@ -242,7 +241,7 @@ fn startup_ethernet() {
         {
             let sockets = &mut *scheduler.sockets().borrow_mut();
             loop {
-                match interface.poll(sockets, board::clock::get_ms()) {
+                match interface.poll(sockets, clock::get_ms()) {
                     Ok(true) => (),
                     Ok(false) => break,
                     Err(smoltcp::Error::Unrecognized) => (),
@@ -284,7 +283,7 @@ pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
             while irq::pending_mask() != 0 {
                 match () {
                     #[cfg(has_timer1)]
-                    () if irq::is_pending(::board::csr::TIMER1_INTERRUPT) =>
+                    () if irq::is_pending(csr::TIMER1_INTERRUPT) =>
                         profiler::sample(pc as usize),
                     _ => panic!("spurious irq {}", irq::pending_mask().trailing_zeros())
                 }
@@ -312,7 +311,7 @@ pub extern fn panic_fmt(args: core::fmt::Arguments, file: &'static str, line: u3
 
     if config::read_str("panic_reset", |r| r == Ok("1")) {
         println!("restarting...");
-        unsafe { board::boot::reset() }
+        unsafe { boot::reset() }
     } else {
         println!("halting.");
         println!("use `artiq_coreconfig write -s panic_reset 1` to restart instead");

artiq/firmware/runtime/mgmt.rs

@@ -1,8 +1,8 @@
 use std::io::{self, Read, Write};
 use log::{self, LevelFilter};
 
+use board_misoc::boot;
 use io::proto::ProtoWrite;
-use board::boot;
 use logger_artiq::BufferLogger;
 use sched::Io;
 use sched::{TcpListener, TcpStream};

artiq/firmware/runtime/moninj.rs

@@ -3,13 +3,12 @@ use std::btree_map::BTreeMap;
 
 use sched::Io;
 use sched::{TcpListener, TcpStream};
-use board::{clock, csr};
+use board_misoc::{clock, csr};
 #[cfg(has_drtio)]
 use drtioaux;
 
 use moninj_proto::*;
 
-
 fn check_magic(stream: &mut TcpStream) -> io::Result<()> {
     const MAGIC: &'static [u8] = b"ARTIQ moninj\n";
 

artiq/firmware/runtime/profiler.rs

@@ -88,7 +88,7 @@ impl Profile {
 
 #[cfg(has_timer1)]
 mod imp {
-    use board::{csr, irq};
+    use board_misoc::{csr, irq};
     use super::{Address, Profile};
 
     static mut PROFILE: Option<Profile> = None;

artiq/firmware/runtime/rtio_mgt.rs

@@ -1,9 +1,9 @@
-use board::{csr, config};
+use board_misoc::{csr, config};
 use sched::Io;
 
 #[cfg(has_rtio_crg)]
 pub mod crg {
-    use board::{clock, csr};
+    use board_misoc::{clock, csr};
 
     pub fn init() {
         unsafe { csr::rtio_crg::pll_reset_write(0) }
@@ -280,7 +280,7 @@ pub fn init_core(phy: bool) {
 
 #[cfg(has_drtio)]
 pub mod drtio_dbg {
-    use board::csr;
+    use board_misoc::csr;
 
     pub fn get_packet_counts(linkno: u8) -> (u32, u32) {
         let linkno = linkno as usize;

artiq/firmware/runtime/sched.rs

@@ -1,17 +1,16 @@
 #![allow(dead_code)]
 
-use std::mem;
+use core::mem;
-use std::result;
+use core::result;
-use std::cell::{Cell, RefCell};
+use core::cell::{Cell, RefCell};
-use std::vec::Vec;
-use std::io::{Read, Write, Result, Error, ErrorKind};
 use fringe::OwnedStack;
 use fringe::generator::{Generator, Yielder, State as GeneratorState};
-
 use smoltcp::wire::IpEndpoint;
 use smoltcp::socket::{SocketHandle, SocketRef};
 
-use board;
+use std::vec::Vec;
+use std::io::{Read, Write, Result, Error, ErrorKind};
+use board_misoc::clock;
 use urc::Urc;
 
 type SocketSet = ::smoltcp::socket::SocketSet<'static, 'static, 'static>;
@@ -128,7 +127,7 @@ impl Scheduler {
         self.threads.append(&mut *self.spawned.borrow_mut());
         if self.threads.len() == 0 { return }
 
-        let now = board::clock::get_ms();
+        let now = clock::get_ms();
         let start_idx = self.run_idx;
         loop {
             self.run_idx = (self.run_idx + 1) % self.threads.len();
@@ -196,7 +195,7 @@ impl<'a> Io<'a> {
 
     pub fn sleep(&self, duration_ms: u64) -> Result<()> {
         let request = WaitRequest {
-            timeout: Some(board::clock::get_ms() + duration_ms),
+            timeout: Some(clock::get_ms() + duration_ms),
             event:   None
         };
 

artiq/firmware/runtime/session.rs

@@ -5,11 +5,11 @@ use std::io::{self, Read, Write};
 use std::error::Error;
 use byteorder::{ByteOrder, NetworkEndian};
 
+use board_misoc::{ident, cache, config};
+use {mailbox, rpc_queue, kernel};
 use urc::Urc;
 use sched::{ThreadHandle, Io};
 use sched::{TcpListener, TcpStream};
-use board::{self, config};
-use {mailbox, rpc_queue, kernel};
 #[cfg(has_rtio_core)]
 use rtio_mgt;
 use rtio_dma::Manager as DmaManager;
@@ -227,7 +227,7 @@ fn process_host_message(io: &Io,
     match host_read(stream)? {
         host::Request::SystemInfo => {
             host_write(stream, host::Reply::SystemInfo {
-                ident: board::ident::read(&mut [0; 64]),
+                ident: ident::read(&mut [0; 64]),
                 finished_cleanly: session.congress.finished_cleanly.get()
             })?;
             session.congress.finished_cleanly.set(true);
@@ -413,7 +413,7 @@ fn process_kern_message(io: &Io, mut stream: Option<&mut TcpStream>,
             }
             &kern::DmaRecordStop { duration } => {
                 session.congress.dma_manager.record_stop(duration);
-                board::cache::flush_l2_cache();
+                cache::flush_l2_cache();
                 kern_acknowledge()
             }
             &kern::DmaEraseRequest { name } => {

artiq/firmware/runtime/watchdog.rs

@@ -1,4 +1,4 @@
-use board::clock;
+use board_misoc::clock;
 
 #[derive(Debug, Clone, Copy)]
 struct Watchdog {

artiq/firmware/satman/Cargo.toml

@@ -15,5 +15,5 @@ build_artiq = { path = "../libbuild_artiq" }
 
 [dependencies]
 log = { version = "0.4", default-features = false }
-board = { path = "../libboard", features = ["uart_console", "log"] }
+board_misoc = { path = "../libboard_misoc", features = ["uart_console", "log"] }
 board_artiq = { path = "../libboard_artiq" }

artiq/firmware/satman/main.rs

@@ -4,10 +4,10 @@
 #[macro_use]
 extern crate log;
 #[macro_use]
-extern crate board;
+extern crate board_misoc;
 extern crate board_artiq;
 
-use board::csr;
+use board_misoc::{csr, ident, clock, uart_logger};
 use board_artiq::{i2c, spi, si5324, drtioaux};
 #[cfg(has_serwb_phy_amc)]
 use board_artiq::serwb;
@@ -67,8 +67,8 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::Result<()> {
             } else if errors & 4 != 0 {
                 let channel;
                 unsafe {
-                    channel = (board::csr::DRTIO[0].busy_channel_read)();
+                    channel = (csr::DRTIO[0].busy_channel_read)();
-                    (board::csr::DRTIO[0].rtio_error_write)(4);
+                    (csr::DRTIO[0].rtio_error_write)(4);
                 }
                 drtioaux::send_link(0,
                     &drtioaux::Packet::RtioErrorBusyReply { channel })
@@ -240,12 +240,12 @@ fn drtio_link_rx_up() -> bool {
 
 #[no_mangle]
 pub extern fn main() -> i32 {
-    board::clock::init();
+    clock::init();
-    board::uart_logger::ConsoleLogger::register();
+    uart_logger::ConsoleLogger::register();
 
     info!("ARTIQ satellite manager starting...");
     info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
-    info!("gateware version {}", board::ident::read(&mut [0; 64]));
+    info!("gateware version {}", ident::read(&mut [0; 64]));
 
     #[cfg(has_serwb_phy_amc)]
     serwb::wait_init();