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phaser/kc705: remove transceiver initialization workaround

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This commit is contained in:
Florent Kermarrec 2016-10-14 19:06:43 +02:00
parent 9ba6be8796
commit 0259c80015
1 changed files with 6 additions and 7 deletions
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artiq/gateware/targets/kc705.py
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@ -467,7 +467,6 @@ class AD9154JESD(Module, AutoCSR):
phy = JESD204BPhyTX( phy = JESD204BPhyTX(
qpll, platform.request("ad9154_jesd", i), fabric_freq) qpll, platform.request("ad9154_jesd", i), fabric_freq)
platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate) platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO
platform.add_false_path_constraints(self.cd_jesd.clk, platform.add_false_path_constraints(self.cd_jesd.clk,
phy.gtx.cd_tx.clk) phy.gtx.cd_tx.clk)
phys.append(phy) phys.append(phy)