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dac_setup: cleanup, add doc

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This commit is contained in:
Robert Jördens 2016-10-06 17:27:50 +02:00
parent fee7831573
commit 01bc7faacc
2 changed files with 15 additions and 5 deletions
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3
README_PHASER.rst
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@ -97,7 +97,8 @@ Usage
----- -----
* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. * An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``.
* run ``artiq_run sawg.py`` for an example that sets up amplitudes, frequencies, * After each boot, run the ``dac_setup.py`` experiment to establish and align the data link (``artiq_run repository/dac_setup.py``).
* run ``artiq_run repository/sawg.py`` for an example that sets up amplitudes, frequencies,
and phases on all four DDS channels. and phases on all four DDS channels.
* Implement your own experiments using the SAWG channels. * Implement your own experiments using the SAWG channels.
* Verify clock stability between the 2 GHz reference clock and the DAC outputs. * Verify clock stability between the 2 GHz reference clock and the DAC outputs.

17
artiq/examples/phaser/repository/dac_setup.py
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@ -38,18 +38,26 @@ class DACSetup(EnvExperiment):
self.ad9154.init() self.ad9154.init()
self.dac_setup() self.dac_setup()
self.ad9154.jesd_prbs(0) self.ad9154.jesd_prbs(0)
t = now_mu() + seconds_to_mu(.1*s) self.busywait_us(200000)
self.ad9154.jesd_enable(1)
while not self.ad9154.jesd_ready():
pass
@kernel
def busywait_us(self, t):
t = now_mu() + seconds_to_mu(t*us)
while self.core.get_rtio_counter_mu() < t: while self.core.get_rtio_counter_mu() < t:
pass pass
self.ad9154.jesd_enable(1)
@kernel @kernel
def dac_setup(self): def dac_setup(self):
# reset # reset
self.ad9154.dac_write(AD9154_SPI_INTFCONFA, AD9154_SOFTRESET_SET(1) | self.ad9154.dac_write(AD9154_SPI_INTFCONFA, AD9154_SOFTRESET_SET(1) |
AD9154_LSBFIRST_SET(0) | AD9154_SDOACTIVE_SET(1)) AD9154_LSBFIRST_SET(0) | AD9154_SDOACTIVE_SET(1))
self.busywait_us(100)
self.ad9154.dac_write(AD9154_SPI_INTFCONFA, self.ad9154.dac_write(AD9154_SPI_INTFCONFA,
AD9154_LSBFIRST_SET(0) | AD9154_SDOACTIVE_SET(1)) AD9154_LSBFIRST_SET(0) | AD9154_SDOACTIVE_SET(1))
self.busywait_us(100)
if ((self.ad9154.dac_read(AD9154_PRODIDH) << 8) | if ((self.ad9154.dac_read(AD9154_PRODIDH) << 8) |
self.ad9154.dac_read(AD9154_PRODIDL) != 0x9154): self.ad9154.dac_read(AD9154_PRODIDL) != 0x9154):
return return
@ -58,6 +66,7 @@ class DACSetup(EnvExperiment):
AD9154_PD_DAC0_SET(0) | AD9154_PD_DAC1_SET(0) | AD9154_PD_DAC0_SET(0) | AD9154_PD_DAC1_SET(0) |
AD9154_PD_DAC2_SET(0) | AD9154_PD_DAC3_SET(0) | AD9154_PD_DAC2_SET(0) | AD9154_PD_DAC3_SET(0) |
AD9154_PD_BG_SET(0)) AD9154_PD_BG_SET(0))
self.busywait_us(100)
self.ad9154.dac_write(AD9154_TXENMASK1, AD9154_DACA_MASK_SET(0) | self.ad9154.dac_write(AD9154_TXENMASK1, AD9154_DACA_MASK_SET(0) |
AD9154_DACB_MASK_SET(0)) # TX not controlled by TXEN pins AD9154_DACB_MASK_SET(0)) # TX not controlled by TXEN pins
self.ad9154.dac_write(AD9154_CLKCFG0, self.ad9154.dac_write(AD9154_CLKCFG0,
@ -228,8 +237,8 @@ class DACSetup(EnvExperiment):
self.ad9154.dac_write(AD9154_VCO_VARACTOR_CTRL_1, self.ad9154.dac_write(AD9154_VCO_VARACTOR_CTRL_1,
AD9154_SPI_VCO_VARACTOR_REF_SET(0x6)) AD9154_SPI_VCO_VARACTOR_REF_SET(0x6))
# ensure link is txing # ensure link is txing
self.ad9154.dac_write(AD9154_SERDESPLL_ENABLE_CNTRL, #self.ad9154.dac_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(1)) # AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(1))
self.ad9154.dac_write(AD9154_SERDESPLL_ENABLE_CNTRL, self.ad9154.dac_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(0)) AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(0))
self.ad9154.dac_write(AD9154_EQ_BIAS_REG, AD9154_EQ_BIAS_RESERVED_SET(0x22) | self.ad9154.dac_write(AD9154_EQ_BIAS_REG, AD9154_EQ_BIAS_RESERVED_SET(0x22) |