From 0127de9bb59fcc91738a66876a616a45cefd7c7c Mon Sep 17 00:00:00 2001 From: Joe Britton Date: Fri, 27 Feb 2015 15:02:28 -0700 Subject: [PATCH] soc: add_cpu_csr_region -> add_csr_region --- soc/targets/artiq_kc705.py | 2 +- soc/targets/artiq_ppro.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index 99d75cb1f..67b080cd3 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -103,7 +103,7 @@ class ARTIQSoC(BaseSoC): rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) - self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs) + self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) dds_pads = platform.request("dds") self.submodules.dds = ad9858.AD9858(dds_pads) diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index c7539e2c2..7d0f9c021 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -122,7 +122,7 @@ class ARTIQMiniSoC(BaseSoC): rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) - self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs) + self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) if with_test_gen: self.submodules.test_gen = _TestGen(platform.request("ttl", 8))