mirror of https://github.com/m-labs/artiq.git
compiler: Extract maximum alignment from target data layout
In particular, i64/double are actually supposed to be aligned to their size on RISC-V (at least according to the ELF psABI), though it is unclear to me whether this actually caused any issues.
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@ -177,6 +177,15 @@ class LLVMIRGenerator:
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self.empty_metadata = self.llmodule.add_metadata([])
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self.quote_fail_msg = None
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# Maximum alignment required according to the target platform ABI. As this is
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# not directly exposed by LLVM, just take the maximum across all the "big"
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# elementary types we use. (Vector types, should we ever support them, are
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# likely contenders for even larger alignment requirements.)
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self.max_target_alignment = max(map(
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lambda t: self.abi_layout_info.get_size_align(t)[1],
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[lli64, lldouble, llptr]
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))
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def add_pred(self, pred, block):
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if block not in self.llpred_map:
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self.llpred_map[block] = set()
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@ -1529,7 +1538,7 @@ class LLVMIRGenerator:
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self.llbuilder.position_at_end(llalloc)
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llalloca = self.llbuilder.alloca(lli8, llsize, name="rpc.alloc")
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llalloca.align = 4 # maximum alignment required by OR1K ABI
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llalloca.align = self.max_target_alignment
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llphi.add_incoming(llalloca, llalloc)
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self.llbuilder.branch(llhead)
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