mirror of https://github.com/m-labs/artiq.git
67 lines
2.0 KiB
Python
67 lines
2.0 KiB
Python
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from artiq.language.core import kernel, delay
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from artiq.language.units import us
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from numpy import int32
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
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0*spi.SPI_INPUT | 1*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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# SPI clock write and read dividers
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SPIT_WR = 4
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SPIT_RD = 16
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SPI_CS = 1
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class Mirny:
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WE = 1 << 24
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kernel_invariants = {"bus", "core", "WE"}
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def __init__(self, dmgr, spi_device, core_device="core"):
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self.core = dmgr.get(core_device)
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self.bus = dmgr.get(spi_device)
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@kernel
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def read_reg(self, addr):
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 24,
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SPIT_RD, SPI_CS)
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self.bus.write((addr << 25))
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return self.bus.read() & int32(0xffff)
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@kernel
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def write_reg(self, addr, data):
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 24, SPIT_WR, SPI_CS)
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self.bus.write((addr << 25) | self.WE | ((data & 0xffff) << 8))
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@kernel
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def init(self):
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reg0 = self.read_reg(0)
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if reg0 & 0b11 != 0b11:
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raise ValueError("Mirny HW_REV mismatch")
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if (reg0 >> 2) & 0b11 != 0b00:
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raise ValueError("Mirny PROTO_REV mismatch")
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delay(100*us) # slack
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@kernel
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def set_att_mu(self, channel, att):
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"""Set digital step attenuator in machine units.
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:param att: Attenuation setting, 8 bit digital.
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 16, SPIT_WR, SPI_CS)
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self.bus.write(((channel | 8) << 25) | (att << 16))
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@kernel
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def write_ext(self, addr, length, data):
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self.bus.set_config_mu(SPI_CONFIG, 8, SPIT_WR, SPI_CS)
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self.bus.write(addr << 25)
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, length,
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SPIT_WR, SPI_CS)
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if length < 32:
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data <<= 32 - length
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self.bus.write(data)
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