2020-08-21 19:31:26 +08:00
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from migen import *
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2020-08-26 23:10:50 +08:00
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from misoc.cores.duc import MultiDDS
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2020-08-21 19:31:26 +08:00
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from artiq.gateware.rtio import rtlink
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2020-08-21 23:21:36 +08:00
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from .fastlink import SerDes, SerInterface
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2020-08-21 19:31:26 +08:00
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2020-08-26 23:10:50 +08:00
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class DDSChannel(Module):
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2020-08-27 01:12:41 +08:00
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def __init__(self, use_lut=None):
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2020-08-26 23:10:50 +08:00
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=4,
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2020-08-27 01:12:41 +08:00
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enable_replace=True))
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to_rio_phy = ClockDomainsRenamer("rio_phy")
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self.submodules.dds = to_rio_phy(MultiDDS(
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n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut))
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# TODO: latency
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self.comb += self.dds.stb.eq(1)
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regs = []
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for i in self.dds.i:
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regs.extend([i.f, Cat(i.a, i.clr, i.p)])
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data)
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)
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]
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2020-08-26 23:10:50 +08:00
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2020-08-21 19:31:26 +08:00
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class Phaser(Module):
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def __init__(self, pins, pins_n):
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2020-08-26 23:10:50 +08:00
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=8, address_width=8,
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enable_replace=False),
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2020-08-22 19:46:41 +08:00
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rtlink.IInterface(data_width=10))
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2020-08-27 01:12:41 +08:00
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self.submodules.ch0 = DDSChannel()
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self.submodules.ch1 = DDSChannel(use_lut=self.ch0.dds.mod.cs.lut)
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n_channels = 2
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n_samples = 8
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n_bits = 14
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2020-08-27 22:26:09 +08:00
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body = Signal(n_samples*n_channels*2*n_bits, reset_less=True)
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2020-08-27 01:12:41 +08:00
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self.sync.rio_phy += [
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If(self.ch0.dds.valid, # & self.ch1.dds.valid,
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2020-08-27 22:26:09 +08:00
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# recent sample, ch0, i first
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Cat(body).eq(Cat(self.ch0.dds.o.i[2:], self.ch0.dds.o.q[2:],
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self.ch1.dds.o.i[2:], self.ch1.dds.o.q[2:],
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body)),
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2020-08-27 01:12:41 +08:00
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),
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]
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2020-08-21 19:31:26 +08:00
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self.submodules.serializer = SerDes(
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2020-08-21 23:21:36 +08:00
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n_data=8, t_clk=8, d_clk=0b00001111,
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n_frame=10, n_crc=6, poly=0x2f)
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self.submodules.intf = SerInterface(pins, pins_n)
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self.comb += [
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Cat(self.intf.data[:-1]).eq(Cat(self.serializer.data[:-1])),
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self.serializer.data[-1].eq(self.intf.data[-1]),
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]
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2020-08-21 19:31:26 +08:00
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header = Record([
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("we", 1),
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("addr", 7),
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("data", 8),
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("type", 4)
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])
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assert len(Cat(header.raw_bits(), body)) == \
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len(self.serializer.payload)
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self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
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2020-08-24 22:49:36 +08:00
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re_dly = Signal(3) # stage, send, respond
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self.sync.rtio += [
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header.type.eq(1), # reserved
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2020-08-21 19:31:26 +08:00
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If(self.serializer.stb,
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header.we.eq(0),
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re_dly.eq(re_dly[1:]),
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2020-08-21 19:31:26 +08:00
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),
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2020-08-26 23:10:50 +08:00
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If(self.rtlink.o.stb,
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re_dly[-1].eq(~self.rtlink.o.address[-1]),
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header.we.eq(self.rtlink.o.address[-1]),
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header.addr.eq(self.rtlink.o.address),
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header.data.eq(self.rtlink.o.data),
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2020-08-21 19:31:26 +08:00
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),
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self.rtlink.i.stb.eq(re_dly[0] & self.serializer.stb),
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self.rtlink.i.data.eq(self.serializer.readback),
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2020-08-21 19:31:26 +08:00
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]
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