mirror of https://github.com/m-labs/artiq.git
37 lines
1.4 KiB
Python
37 lines
1.4 KiB
Python
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from migen.fhdl.std import *
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from artiq.gateware import ad9858 as ad9858_ll
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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class AD9858(Module):
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def __init__(self, pads, nchannels=8, **kwargs):
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self.submodules._ll = RenameClockDomains(
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ad9858_ll.AD9858(pads, **kwargs), "rio")
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self.submodules._rt2wb = RT2WB(7, self._ll.bus)
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self.rtlink = self._rt2wb.rtlink
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self.probes = [Signal(32) for i in range(nchannels)]
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# # #
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# keep track of the currently selected channel
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current_channel = Signal(max=nchannels)
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self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 65),
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current_channel.eq(self.rtlink.o.data))
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# keep track of frequency tuning words, before they are FUDed
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ftws = [Signal(32) for i in range(nchannels)]
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for i in range(4):
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for c, ftw in enumerate(ftws):
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self.sync.rio += \
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If(self.rtlink.o.stb & \
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(self.rtlink.o.address == 0x0a+i) & \
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(current_channel == c),
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ftw[i*8:(i+1)*8].eq(self.rtlink.o.data)
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)
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# FTW to probe on FUD
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for c, (probe, ftw) in enumerate(zip(self.probes, ftw)):
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fud = self.rtlink.o.stb & (self.rtlink.o.address == 64)
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self.sync.rio += If(fud & (current_channel == c), probe.eq(ftw))
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