mirror of https://github.com/m-labs/artiq.git
63 lines
1.5 KiB
Python
63 lines
1.5 KiB
Python
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from migen.fhdl.std import *
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class OInterface:
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def __init__(self, data_width, address_width=0,
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fine_ts_width=0, latency=1, suppress_nop=True):
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self.stb = Signal()
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self.busy = Signal()
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if data_width:
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self.data = Signal(data_width)
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if address_width:
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self.address = Signal(address_width)
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if fine_ts_width:
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self.fine_ts = Signal(fine_ts_width)
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self.latency = latency
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self.suppress_nop = suppress_nop
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class IInterface:
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def __init__(self, data_width,
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timestamped=True, fine_ts_width=0, latency=2):
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self.stb = Signal()
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if data_width:
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self.data = Signal(data_width)
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if fine_ts_width:
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self.fine_ts = Signal(fine_ts_width)
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self.latency = latency
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self.timestamped = timestamped
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assert(not fine_ts_width or timestamped)
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class Interface:
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def __init__(self, o, i=None):
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self.o = o
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self.i = i
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def _get_or_zero(interface, attr):
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if isinstance(interface, Interface):
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return max(_get_or_zero(interface.i, attr),
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_get_or_zero(interface.o, attr))
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else:
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if hasattr(interface, attr):
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return flen(getattr(interface, attr))
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else:
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return 0
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def get_data_width(interface):
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return _get_or_zero(interface, "data")
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def get_address_width(interface):
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return _get_or_zero(interface, "address")
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def get_fine_ts_width(interface):
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return _get_or_zero(interface, "fine_ts")
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