artiq/artiq/gateware/targets/sayma_amc_standalone.py

#!/usr/bin/env python3

import argparse

from migen import *

from misoc.cores import gpio
from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
from misoc.integration.builder import builder_args, builder_argdict
from misoc.interconnect import stream
from misoc.targets.sayma_amc import MiniSoC

from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import serwb
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple
from artiq import __version__ as artiq_version


class SaymaAMCStandalone(MiniSoC, AMPSoC):
    mem_map = {
        "cri_con":       0x10000000,
        "rtio":          0x20000000,
        "rtio_dma":      0x30000000,
        "serwb":         0x20000000,
        "mailbox":       0x70000000
    }
    mem_map.update(MiniSoC.mem_map)

    def __init__(self, cpu_type="or1k", **kwargs):
        MiniSoC.__init__(self,
                         cpu_type=cpu_type,
                         sdram_controller_type="minicon",
                         l2_size=128*1024,
                         ident=artiq_version,
                         ethmac_nrxslots=4,
                         ethmac_ntxslots=4,
                         **kwargs)
        AMPSoC.__init__(self)
        platform = self.platform
        platform.toolchain.bitstream_commands.append(
            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")

        self.submodules.leds = gpio.GPIOOut(Cat(
            platform.request("user_led", 0),
            platform.request("user_led", 1)))
        self.csr_devices.append("leds")

        # forward RTM UART to second FTDI UART channel
        serial_1 = platform.request("serial", 1)
        serial_rtm = platform.request("serial_rtm")
        self.comb += [
            serial_1.tx.eq(serial_rtm.rx),
            serial_rtm.tx.eq(serial_1.rx)
        ]

        # AMC/RTM serwb
        # TODO: cleanup (same comments as in sayma_rtm.py)
        serwb_pll = serwb.kusphy.KUSSerdesPLL(self.clk_freq, 1.25e9, vco_div=2)
        self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
        self.submodules += serwb_pll

        serwb_pads = platform.request("amc_rtm_serwb")
        serwb_serdes = serwb.kusphy.KUSSerdes(serwb_pll, serwb_pads, mode="master")
        self.submodules += serwb_serdes
        serwb_init = serwb.phy.SerdesMasterInit(serwb_serdes, taps=512)
        self.submodules += serwb_init
        self.submodules.serwb_control = serwb.phy.SerdesControl(serwb_init, mode="master")
        self.csr_devices.append("serwb_control")

        serwb_serdes.cd_serdes.clk.attr.add("keep")
        serwb_serdes.cd_serdes_20x.clk.attr.add("keep")
        serwb_serdes.cd_serdes_5x.clk.attr.add("keep")
        platform.add_period_constraint(serwb_serdes.cd_serdes.clk, 32.0),
        platform.add_period_constraint(serwb_serdes.cd_serdes_20x.clk, 1.6),
        platform.add_period_constraint(serwb_serdes.cd_serdes_5x.clk, 6.4)
        platform.add_false_path_constraints(
            self.crg.cd_sys.clk,
            serwb_serdes.cd_serdes.clk,
            serwb_serdes.cd_serdes_5x.clk)

        serwb_depacketizer = serwb.packet.Depacketizer(self.clk_freq)
        serwb_packetizer = serwb.packet.Packetizer()
        self.submodules += serwb_depacketizer, serwb_packetizer
        serwb_etherbone = serwb.etherbone.Etherbone(mode="slave")
        self.submodules += serwb_etherbone
        serwb_tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(
            stream.AsyncFIFO([("data", 32)], 8))
        self.submodules += serwb_tx_cdc
        serwb_rx_cdc = ClockDomainsRenamer({"write": "serdes", "read": "sys"})(
            stream.AsyncFIFO([("data", 32)], 8))
        self.submodules += serwb_rx_cdc
        self.comb += [
            # core <--> etherbone
            serwb_depacketizer.source.connect(serwb_etherbone.sink),
            serwb_etherbone.source.connect(serwb_packetizer.sink),

            # core --> serdes
            serwb_packetizer.source.connect(serwb_tx_cdc.sink),
            If(serwb_tx_cdc.source.stb & serwb_init.ready,
                serwb_serdes.tx_data.eq(serwb_tx_cdc.source.data)
            ),
            serwb_tx_cdc.source.ack.eq(serwb_init.ready),

            # serdes --> core
            serwb_rx_cdc.sink.stb.eq(serwb_init.ready),
            serwb_rx_cdc.sink.data.eq(serwb_serdes.rx_data),
            serwb_rx_cdc.source.connect(serwb_depacketizer.sink),
        ]
        self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_etherbone.wishbone.bus)

        # RTIO
        rtio_channels = []
        for i in (2, 3):
            phy = ttl_simple.Output(platform.request("user_led", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))

        for i in (0, 1):
            sma_io = platform.request("sma_io", i)
            self.comb += sma_io.direction.eq(1)
            phy = ttl_simple.Output(sma_io.level)
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(phy))

        self.config["HAS_RTIO_LOG"] = None
        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
        rtio_channels.append(rtio.LogChannel())

        self.clock_domains.cd_rtio = ClockDomain()
        self.comb += [
            self.cd_rtio.clk.eq(ClockSignal()),
            self.cd_rtio.rst.eq(ResetSignal())
        ]
        self.submodules.rtio_core = rtio.Core(rtio_channels)
        self.csr_devices.append("rtio_core")
        self.submodules.rtio = rtio.KernelInitiator()
        self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
            rtio.DMA(self.get_native_sdram_if()))
        self.register_kernel_cpu_csrdevice("rtio")
        self.register_kernel_cpu_csrdevice("rtio_dma")
        self.submodules.cri_con = rtio.CRIInterconnectShared(
            [self.rtio.cri, self.rtio_dma.cri],
            [self.rtio_core.cri])
        self.register_kernel_cpu_csrdevice("cri_con")
        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
        self.csr_devices.append("rtio_moninj")

        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
                                                      self.get_native_sdram_if())
        self.csr_devices.append("rtio_analyzer")


def main():
    parser = argparse.ArgumentParser(
        description="ARTIQ device binary builder / Sayma AMC stand-alone")
    builder_args(parser)
    soc_sdram_args(parser)
    args = parser.parse_args()

    soc = SaymaAMCStandalone(**soc_sdram_argdict(args))
    build_artiq_soc(soc, builder_argdict(args))


if __name__ == "__main__":
    main()