2017-06-18 12:45:07 +08:00
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pub mod i2c {
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use ::send;
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use ::recv;
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use kernel_proto::*;
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pub extern fn start(busno: i32) {
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send(&I2cStartRequest { busno: busno as u8 });
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2017-06-19 14:22:59 +08:00
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recv!(&I2cBasicReply { succeeded } => if !succeeded {
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raise!("I2CError", "I2C bus could not be accessed");
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});
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2017-06-18 12:45:07 +08:00
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}
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pub extern fn stop(busno: i32) {
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send(&I2cStopRequest { busno: busno as u8 });
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2017-06-19 14:22:59 +08:00
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recv!(&I2cBasicReply { succeeded } => if !succeeded {
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raise!("I2CError", "I2C bus could not be accessed");
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});
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2017-06-18 12:45:07 +08:00
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}
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pub extern fn write(busno: i32, data: i32) -> bool {
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send(&I2cWriteRequest { busno: busno as u8, data: data as u8 });
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2017-06-19 14:22:59 +08:00
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recv!(&I2cWriteReply { succeeded, ack } => {
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if !succeeded {
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raise!("I2CError", "I2C bus could not be accessed");
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}
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ack
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})
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2017-06-18 12:45:07 +08:00
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}
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pub extern fn read(busno: i32, ack: bool) -> i32 {
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send(&I2cReadRequest { busno: busno as u8, ack: ack });
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2017-06-19 14:22:59 +08:00
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recv!(&I2cReadReply { succeeded, data } => {
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if !succeeded {
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raise!("I2CError", "I2C bus could not be accessed");
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}
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data
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}) as i32
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2017-06-18 12:45:07 +08:00
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}
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}
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pub mod spi {
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use ::send;
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use ::recv;
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use kernel_proto::*;
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pub extern fn set_config(busno: i32, flags: i32, write_div: i32, read_div: i32) {
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send(&SpiSetConfigRequest { busno: busno as u32, flags: flags as u8,
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write_div: write_div as u8, read_div: read_div as u8 });
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2017-06-19 14:22:59 +08:00
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recv!(&SpiBasicReply { succeeded } => if !succeeded {
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raise!("SPIError", "SPI bus could not be accessed");
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});
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2017-06-18 12:45:07 +08:00
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}
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pub extern fn set_xfer(busno: i32, chip_select: i32, write_length: i32, read_length: i32) {
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send(&SpiSetXferRequest { busno: busno as u32, chip_select: chip_select as u16,
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write_length: write_length as u8, read_length: read_length as u8 });
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2017-06-19 14:22:59 +08:00
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recv!(&SpiBasicReply { succeeded } => if !succeeded {
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raise!("SPIError", "SPI bus could not be accessed");
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});
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2017-06-18 12:45:07 +08:00
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}
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pub extern fn write(busno: i32, data: i32) {
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send(&SpiWriteRequest { busno: busno as u32, data: data as u32 });
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2017-06-19 14:22:59 +08:00
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recv!(&SpiBasicReply { succeeded } => if !succeeded {
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raise!("SPIError", "SPI bus could not be accessed");
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});
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2017-06-18 12:45:07 +08:00
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}
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pub extern fn read(busno: i32) -> i32 {
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send(&SpiReadRequest { busno: busno as u32 });
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2017-06-19 14:22:59 +08:00
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recv!(&SpiReadReply { succeeded, data } => {
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if !succeeded {
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raise!("SPIError", "SPI bus could not be accessed");
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}
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data
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}) as i32
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2017-06-18 12:45:07 +08:00
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}
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}
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