mirror of https://github.com/m-labs/artiq.git
62 lines
1.6 KiB
Python
62 lines
1.6 KiB
Python
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core_addr = "sayma-1.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"fmcdio_dirctl_clk": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 6}
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},
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"fmcdio_dirctl_ser": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 7}
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},
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"fmcdio_dirctl_latch": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 8}
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},
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"fmcdio_dirctl": {
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"type": "local",
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"module": "artiq.coredevice.shiftreg",
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"class": "ShiftReg",
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"arguments": {"clk": "fmcdio_dirctl_clk",
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"ser": "fmcdio_dirctl_ser",
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"latch": "fmcdio_dirctl_latch"}
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},
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}
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for i in range(8):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 9+i},
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}
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