69 lines
1.7 KiB
Rust
69 lines
1.7 KiB
Rust
#![no_std]
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#![feature(never_type)]
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extern crate log;
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extern crate crc;
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extern crate embedded_hal;
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extern crate core_io;
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extern crate io;
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extern crate libboard_zynq;
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extern crate libregister;
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extern crate libconfig;
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extern crate libcortex_a9;
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extern crate libasync;
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extern crate log_buffer;
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#[path = "../../../build/pl.rs"]
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pub mod pl;
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pub mod drtioaux_proto;
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pub mod drtio_routing;
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pub mod logger;
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#[cfg(has_si5324)]
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pub mod si5324;
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#[cfg(has_drtio)]
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pub mod drtioaux;
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#[cfg(has_drtio)]
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pub mod drtioaux_async;
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#[cfg(has_drtio)]
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#[path = "../../../build/mem.rs"]
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pub mod mem;
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use core::{cmp, str};
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use libboard_zynq::slcr;
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use libregister::RegisterW;
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pub fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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let len = pl::csr::identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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pl::csr::identifier::address_write(1 + i);
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buf[i as usize] = pl::csr::identifier::data_read();
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}
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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pub fn init_gateware() {
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// Set up PS->PL clocks
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slcr::RegisterBlock::unlocked(|slcr| {
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// As we are touching the mux, the clock may glitch, so reset the PL.
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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slcr.fpga0_clk_ctrl.write(
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slcr::Fpga0ClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor0(8)
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.divisor1(1)
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);
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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);
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});
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} |