127 lines
4.2 KiB
Python
127 lines
4.2 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg, AsyncResetSynchronizer, PulseSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr_eventmanager import *
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from ddmtd import DDMTDSamplerGTX, DDMTD
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, counter_width=24, domains=["gtx0_rtio_rx", "sys", "helper"]):
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for domain in domains:
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name = "counter_" + domain
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counter = CSRStatus(counter_width, name=name)
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setattr(self, name, counter)
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self.update_en = CSRStorage()
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timer = Signal(counter_width)
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timer_tick = Signal()
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self.sync += Cat(timer, timer_tick).eq(timer + 1)
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for domain in domains:
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sync_domain = getattr(self.sync, domain)
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divider = Signal(2)
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sync_domain += divider.eq(divider + 1)
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divided = Signal()
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divided.attr.add("no_retiming")
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sync_domain += divided.eq(divider[-1])
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divided_sys = Signal()
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self.specials += MultiReg(divided, divided_sys)
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divided_sys_r = Signal()
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divided_tick = Signal()
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self.sync += divided_sys_r.eq(divided_sys)
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self.comb += divided_tick.eq(divided_sys & ~divided_sys_r)
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counter = Signal(counter_width)
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counter_csr = getattr(self, "counter_" + domain)
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self.sync += [
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If(timer_tick,
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If(self.update_en.storage, counter_csr.status.eq(counter)),
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counter.eq(0),
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).Else(
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If(divided_tick, counter.eq(counter + 1))
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)
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]
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class WRPLL(Module, AutoCSR):
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def __init__(self, gtx, main_dcxo_pads, helper_dcxo_pads, COUNTER_BIT=32):
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self.gtx_tag = CSRStatus(COUNTER_BIT)
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self.main_tag = CSRStatus(COUNTER_BIT)
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ddmtd_counter = Signal(COUNTER_BIT)
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gtx_tag_sys = Signal(COUNTER_BIT)
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main_tag_sys = Signal(COUNTER_BIT)
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gtx_tag_stb_sys = Signal()
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main_tag_stb_sys = Signal()
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# # #
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self.helper_reset = CSRStorage(reset=1)
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self.clock_domains.cd_helper = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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self.specials += [
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Instance("IBUFGDS",
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i_I=helper_dcxo_pads.p, i_IB=helper_dcxo_pads.n,
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o_O=self.cd_helper.clk),
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AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
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]
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self.submodules.frequency_counter = FrequencyCounter()
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self.submodules.ddmtd_sampler = DDMTDSamplerGTX(gtx, main_dcxo_pads)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_gtx = DDMTD(ddmtd_counter, self.ddmtd_sampler.gtx_beating)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, self.ddmtd_sampler.main_beating)
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# DDMTD tags collection
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self.specials += [
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MultiReg(self.ddmtd_gtx.h_tag, gtx_tag_sys),
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MultiReg(self.ddmtd_main.h_tag, main_tag_sys)
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]
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gtx_tag_stb_ps = PulseSynchronizer("helper", "sys")
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main_tag_stb_ps = PulseSynchronizer("helper", "sys")
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self.submodules += [
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gtx_tag_stb_ps,
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main_tag_stb_ps
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]
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self.sync.helper += [
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gtx_tag_stb_ps.i.eq(self.ddmtd_gtx.h_tag_update),
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main_tag_stb_ps.i.eq(self.ddmtd_main.h_tag_update)
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]
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self.sync += [
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gtx_tag_stb_sys.eq(gtx_tag_stb_ps.o),
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main_tag_stb_sys.eq(main_tag_stb_ps.o)
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]
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self.sync += [
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If(gtx_tag_stb_sys,
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self.gtx_tag.status.eq(gtx_tag_sys),
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),
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If(main_tag_stb_sys,
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self.main_tag.status.eq(main_tag_sys)
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)
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]
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# PL-PS shared peripheral interrupt (SPI)
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self.submodules.gtx_tag_ev = EventManager()
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self.gtx_tag_ev.stb = EventSourcePulse()
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self.gtx_tag_ev.finalize()
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self.submodules.main_tag_ev = EventManager()
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self.main_tag_ev.stb = EventSourcePulse()
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self.main_tag_ev.finalize()
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self.sync += [
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self.gtx_tag_ev.stb.trigger.eq(gtx_tag_stb_sys),
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self.main_tag_ev.stb.trigger.eq(main_tag_stb_sys)
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]
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