123 lines
3.2 KiB
Rust
123 lines
3.2 KiB
Rust
use log::{info, warn};
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use libboard_zynq::{timer::GlobalTimer};
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use embedded_hal::blocking::delay::DelayMs;
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use libconfig::Config;
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use libboard_artiq::pl;
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use crate::i2c;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[allow(non_camel_case_types)]
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pub enum RtioClock {
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Int_125,
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Int_100,
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Int_150,
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Ext0_Bypass,
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Ext0_Synth0_10to125,
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Ext0_Synth0_100to125,
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Ext0_Synth0_125to125,
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}
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fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
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if let Ok(clk) = cfg.read_str("rtio_clock") {
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match clk.as_ref() {
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"int_125" => RtioClock::Int_125,
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"int_100" => RtioClock::Int_100,
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"int_150" => RtioClock::Int_150,
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"ext0_bypass" => RtioClock::Ext0_Bypass,
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"ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125,
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"ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125,
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"ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
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_ => RtioClock::Int_125
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}
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}
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else {
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RtioClock::Int_125
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}
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}
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fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
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#[cfg(has_rtio_crg_clock_sel)]
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let clock_sel = match _clk {
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RtioClock::Ext0_Bypass => {
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info!("using bypassed external clock");
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1
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},
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x => {
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info!("using clock: {:?}", x);
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0
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}
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};
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loop {
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unsafe {
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pl::csr::rtio_crg::pll_reset_write(1);
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#[cfg(has_rtio_crg_clock_sel)]
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pl::csr::rtio_crg::clock_sel_write(clock_sel);
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pl::csr::rtio_crg::pll_reset_write(0);
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}
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timer.delay_ms(1);
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let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
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if locked {
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info!("RTIO PLL locked");
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break;
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} else {
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warn!("RTIO PLL failed to lock, retrying...");
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timer.delay_ms(500);
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}
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}
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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}
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}
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#[cfg(has_drtio)]
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fn init_drtio(timer: &mut GlobalTimer)
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{
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unsafe {
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pl::csr::drtio_transceiver::stable_clkin_write(1);
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}
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timer.delay_ms(2); // wait for CPLL/QPLL lock
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unsafe {
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pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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#[cfg(has_si5324)]
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fn setup_si5324(timer: &mut GlobalTimer, clk: RtioClock) {
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let mut si5324_settings: Option<si5324::FrequencySettings> = None;
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// 125MHz output, from crystal, 7 Hz
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if si5324_settings.is_none() || clk == RtioClock::Int_125 {
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info!("using internal 125MHz RTIO clock");
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si5324_settings = Some(si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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});
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}
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si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
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&si5324_settings.unwrap(), si5324::Input::Ckin2, timer).expect("cannot initialize Si5324");
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}
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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let clk = get_rtio_clock_cfg(cfg);
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#[cfg(has_si5324)]
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setup_si5324(timer, clk);
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#[cfg(has_drtio)]
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init_drtio(timer);
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init_rtio(timer, clk);
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} |