690 lines
27 KiB
Python
Executable File
690 lines
27 KiB
Python
Executable File
#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zc706
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.cores import gpio
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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import dma
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import analyzer
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import acpki
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import drtio_aux_controller
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self.clock_sel = CSRStorage()
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self.clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
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# This also changes the I/O standard for some on-board LEDs.
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leds_fmc33 = [
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("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
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("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
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("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
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("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
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]
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# same deal as with LEDs - changed I/O standard.
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si5324_fmc33 = [
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("si5324_33", 0,
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Subsignal("rst_n", Pins("W23"), IOStandard("LVCMOS33")),
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Subsignal("int", Pins("AJ25"), IOStandard("LVCMOS33"))
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),
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]
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def prepare_zc706_platform(platform):
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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class ZC706(SoCCore):
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def __init__(self, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg_clock_sel"] = None
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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class _MasterBase(SoCCore):
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def __init__(self, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_extension(si5324_fmc33)
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self.sys_clk_freq = 125e6
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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data_pads = [
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platform.request("sfp"),
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platform.request("user_sma_mgt")
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]
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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sys_clk_freq=self.sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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mem_size = coreaux.get_mem_size()
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
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self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_as_synthesizer"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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gtx0.txoutclk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# (Each channel performs single-lane phase alignment for RX)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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class _SatelliteBase(SoCCore):
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def __init__(self, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_extension(si5324_fmc33)
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self.sys_clk_freq = 125e6
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platform = self.platform
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# SFP
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self.comb += platform.request("sfp_tx_disable_n").eq(0)
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data_pads = [
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platform.request("sfp"),
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platform.request("user_sma_mgt")
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]
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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sys_clk_freq=self.sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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# Satellite
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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# Repeaters
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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mem_size = coreaux.get_mem_size()
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tx_port = coreaux.get_tx_port()
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rx_port = coreaux.get_rx_port()
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memory_address = self.axi2csr.register_port(tx_port, mem_size)
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# rcv in upper half of the memory, thus added second
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self.axi2csr.register_port(rx_port, mem_size)
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# and registered in PS interface
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# manually, because software refers to rx/tx by halves of entire memory block, not names
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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# Si5324 Phaser
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_siphaser"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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gtx0.txoutclk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# (Each channel performs single-lane phase alignment for RX)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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|
self.ps7.cd_sys.clk, gtx.rxoutclk)
|
|
|
|
self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
|
|
self.csr_devices.append("rtio_crg")
|
|
fix_serdes_timing_path(self.platform)
|
|
|
|
def add_rtio(self, rtio_channels):
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
if self.acpki:
|
|
self.rustc_cfg["ki_impl"] = "acp"
|
|
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
|
bus=self.ps7.s_axi_acp,
|
|
user=self.ps7.s_axi_acp_user,
|
|
evento=self.ps7.event.o)
|
|
self.csr_devices.append("rtio")
|
|
else:
|
|
self.rustc_cfg["ki_impl"] = "csr"
|
|
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
|
|
self.csr_devices.append("rtio")
|
|
|
|
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.drtiosat.cri],
|
|
[self.local_io.cri] + self.drtio_cri,
|
|
mode="sync", enable_routing=True)
|
|
self.csr_devices.append("cri_con")
|
|
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
|
|
# This also changes the I/O standard for some on-board LEDs.
|
|
leds_fmc33 = [
|
|
("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
|
|
("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
|
|
("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
|
|
("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
|
|
]
|
|
|
|
# todo: verify if gpio pins/expansion port on xadc is the same as on kc705
|
|
_ams101_dac = [
|
|
("ams101_dac", 0,
|
|
Subsignal("ldac", Pins("XADC:GPIO0")),
|
|
Subsignal("clk", Pins("XADC:GPIO1")),
|
|
Subsignal("mosi", Pins("XADC:GPIO2")),
|
|
Subsignal("cs_n", Pins("XADC:GPIO3")),
|
|
IOStandard("LVTTL")
|
|
)
|
|
]
|
|
|
|
_sdcard_spi_33 = [
|
|
("sdcard_spi_33", 0,
|
|
Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")),
|
|
Subsignal("clk", Pins("B20")),
|
|
Subsignal("mosi", Pins("J18")),
|
|
Subsignal("cs_n", Pins("H18")),
|
|
IOStandard("LVCMOS33")
|
|
)
|
|
]
|
|
|
|
class _NIST_CLOCK_RTIO:
|
|
"""
|
|
NIST clock hardware, with old backplane and 11 DDS channels
|
|
"""
|
|
def __init__(self):
|
|
platform = self.platform
|
|
platform.add_extension(nist_clock.fmc_adapter_io)
|
|
platform.add_extension(leds_fmc33)
|
|
platform.add_extension(_ams101_dac)
|
|
platform.add_extension(_sdcard_spi_33)
|
|
|
|
rtio_channels = []
|
|
|
|
for i in range(16):
|
|
if i % 4 == 3:
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
else:
|
|
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
for i in range(2):
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
# todo: figure out what to do since zc706 has no SMA I/O
|
|
# phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
|
|
# self.submodules += phy
|
|
# rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
# could check the LED #
|
|
phy = ttl_simple.Output(platform.request("user_led_33", 2))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
ams101_dac = self.platform.request("ams101_dac", 0)
|
|
phy = ttl_simple.Output(ams101_dac.ldac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
phy = ttl_simple.ClockGen(platform.request("la32_p"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
phy = spi2.SPIMaster(ams101_dac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
for i in range(3):
|
|
phy = spi2.SPIMaster(self.platform.request("spi", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=128))
|
|
|
|
phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
|
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(rtio_channels)
|
|
|
|
|
|
class _NIST_QC2_RTIO:
|
|
"""
|
|
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
|
|
and 24 DDS channels. Two backplanes are used.
|
|
"""
|
|
def __init__(self):
|
|
platform = self.platform
|
|
platform.add_extension(nist_qc2.fmc_adapter_io)
|
|
platform.add_extension(leds_fmc33)
|
|
platform.add_extension(_ams101_dac)
|
|
|
|
rtio_channels = []
|
|
|
|
# All TTL channels are In+Out capable
|
|
for i in range(40):
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
# phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
|
|
# self.submodules += phy
|
|
# rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
phy = ttl_simple.Output(platform.request("user_led_33", 2))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
ams101_dac = self.platform.request("ams101_dac", 0)
|
|
phy = ttl_simple.Output(ams101_dac.ldac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
# CLK0, CLK1 are for clock generators, on backplane SMP connectors
|
|
for i in range(2):
|
|
phy = ttl_simple.ClockGen(
|
|
platform.request("clkout", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
phy = spi2.SPIMaster(ams101_dac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
for i in range(4):
|
|
phy = spi2.SPIMaster(self.platform.request("spi", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=128))
|
|
|
|
for backplane_offset in range(2):
|
|
phy = dds.AD9914(
|
|
platform.request("dds", backplane_offset), 12, onehot=True)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
|
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(rtio_channels)
|
|
|
|
|
|
class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
|
|
def __init__(self, acpki):
|
|
ZC706.__init__(self, acpki)
|
|
_NIST_CLOCK_RTIO.__init__(self)
|
|
|
|
class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
|
|
def __init__(self, acpki):
|
|
_MasterBase.__init__(self, acpki)
|
|
|
|
_NIST_CLOCK_RTIO.__init__(self)
|
|
|
|
class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
|
|
def __init__(self, acpki):
|
|
_SatelliteBase.__init__(self, acpki)
|
|
_NIST_CLOCK_RTIO.__init__(self)
|
|
|
|
class NIST_QC2(ZC706, _NIST_QC2_RTIO):
|
|
def __init__(self, acpki):
|
|
ZC706.__init__(self, acpki)
|
|
_NIST_QC2_RTIO.__init__(self)
|
|
|
|
class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
|
|
def __init__(self, acpki):
|
|
_MasterBase.__init__(self, acpki)
|
|
_NIST_QC2_RTIO.__init__(self)
|
|
|
|
class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
|
|
def __init__(self, acpki):
|
|
_SatelliteBase.__init__(self, acpki)
|
|
_NIST_QC2_RTIO.__init__(self)
|
|
|
|
|
|
VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
|
|
NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
|
|
|
|
|
|
def write_csr_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
f.write(cpu_interface.get_csr_rust(
|
|
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
|
|
|
|
def write_mem_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
f.write(cpu_interface.get_mem_rust(
|
|
soc.get_memory_regions(), soc.get_memory_groups(), None))
|
|
|
|
|
|
def write_rustc_cfg_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
|
|
if v is None:
|
|
f.write("{}\n".format(k))
|
|
else:
|
|
f.write("{}=\"{}\"\n".format(k, v))
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="ARTIQ port to the ZC706 Zynq development kit")
|
|
parser.add_argument("-r", default=None,
|
|
help="build Rust interface into the specified file")
|
|
parser.add_argument("-m", default=None,
|
|
help="build Rust memory interface into the specified file")
|
|
parser.add_argument("-c", default=None,
|
|
help="build Rust compiler configuration into the specified file")
|
|
parser.add_argument("-g", default=None,
|
|
help="build gateware into the specified directory")
|
|
parser.add_argument("-V", "--variant", default="nist_clock",
|
|
help="variant: "
|
|
"[acpki_]nist_clock/nist_qc2[_master/_satellite] "
|
|
"(default: %(default)s)")
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
acpki = variant.startswith("acpki_")
|
|
if acpki:
|
|
variant = variant[6:]
|
|
try:
|
|
cls = VARIANTS[variant]
|
|
except KeyError:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
|
|
soc = cls(acpki=acpki)
|
|
soc.finalize()
|
|
|
|
if args.r is not None:
|
|
write_csr_file(soc, args.r)
|
|
if args.m is not None:
|
|
write_mem_file(soc, args.m)
|
|
if args.c is not None:
|
|
write_rustc_cfg_file(soc, args.c)
|
|
if args.g is not None:
|
|
soc.build(build_dir=args.g)
|
|
|
|
if __name__ == "__main__":
|
|
main()
|