627 lines
22 KiB
Rust
627 lines
22 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(never_type, panic_info_message, asm, naked_functions)]
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#![feature(alloc_error_handler)]
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#[macro_use]
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extern crate log;
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extern crate embedded_hal;
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extern crate libboard_zynq;
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extern crate libboard_artiq;
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extern crate libsupport_zynq;
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extern crate libcortex_a9;
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extern crate libregister;
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extern crate unwind;
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extern crate alloc;
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
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use libsupport_zynq::ram;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, init_gateware};
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use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
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use libregister::{RegisterW, RegisterR};
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use embedded_hal::blocking::delay::DelayUs;
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use core::sync::atomic::{AtomicBool, Ordering};
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mod repeater;
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fn drtiosat_reset(reset: bool) {
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unsafe {
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csr::drtiosat::reset_write(if reset { 1 } else { 0 });
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}
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}
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fn drtiosat_reset_phy(reset: bool) {
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unsafe {
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csr::drtiosat::reset_phy_write(if reset { 1 } else { 0 });
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}
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}
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fn drtiosat_link_rx_up() -> bool {
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unsafe {
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csr::drtiosat::rx_up_read() == 1
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}
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}
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fn drtiosat_tsc_loaded() -> bool {
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unsafe {
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let tsc_loaded = csr::drtiosat::tsc_loaded_read() == 1;
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if tsc_loaded {
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csr::drtiosat::tsc_loaded_write(1);
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}
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tsc_loaded
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}
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}
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#[cfg(has_drtio_routing)]
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macro_rules! forward {
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($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {{
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let hop = $routing_table.0[$destination as usize][$rank as usize];
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if hop != 0 {
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let repno = (hop - 1) as usize;
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if repno < $repeaters.len() {
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return $repeaters[repno].aux_forward($packet, $timer);
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} else {
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return Err(drtioaux::Error::RoutingError);
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}
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}
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}}
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}
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#[cfg(not(has_drtio_routing))]
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macro_rules! forward {
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($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {}
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}
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fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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_routing_table: &mut drtio_routing::RoutingTable, _rank: &mut u8,
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packet: drtioaux::Packet, timer: &mut GlobalTimer, i2c: &mut I2c) -> Result<(), drtioaux::Error> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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match packet {
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drtioaux::Packet::EchoRequest =>
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drtioaux::send(0, &drtioaux::Packet::EchoReply),
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drtioaux::Packet::ResetRequest => {
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info!("resetting RTIO");
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drtiosat_reset(true);
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timer.delay_us(100);
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drtiosat_reset(false);
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for rep in _repeaters.iter() {
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if let Err(e) = rep.rtio_reset(timer) {
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error!("failed to issue RTIO reset ({:?})", e);
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}
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}
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drtioaux::send(0, &drtioaux::Packet::ResetAck)
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},
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drtioaux::Packet::DestinationStatusRequest { destination: _destination } => {
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#[cfg(has_drtio_routing)]
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let hop = _routing_table.0[_destination as usize][*_rank as usize];
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#[cfg(not(has_drtio_routing))]
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let hop = 0;
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if hop == 0 {
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let errors;
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unsafe {
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errors = csr::drtiosat::rtio_error_read();
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}
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if errors & 1 != 0 {
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let channel;
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unsafe {
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channel = csr::drtiosat::sequence_error_channel_read();
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csr::drtiosat::rtio_error_write(1);
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}
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drtioaux::send(0,
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&drtioaux::Packet::DestinationSequenceErrorReply { channel })?;
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} else if errors & 2 != 0 {
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let channel;
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unsafe {
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channel = csr::drtiosat::collision_channel_read();
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csr::drtiosat::rtio_error_write(2);
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}
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drtioaux::send(0,
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&drtioaux::Packet::DestinationCollisionReply { channel })?;
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} else if errors & 4 != 0 {
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let channel;
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unsafe {
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channel = csr::drtiosat::busy_channel_read();
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csr::drtiosat::rtio_error_write(4);
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}
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drtioaux::send(0,
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&drtioaux::Packet::DestinationBusyReply { channel })?;
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}
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else {
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drtioaux::send(0, &drtioaux::Packet::DestinationOkReply)?;
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}
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}
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#[cfg(has_drtio_routing)]
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{
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if hop != 0 {
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let hop = hop as usize;
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if hop <= csr::DRTIOREP.len() {
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let repno = hop - 1;
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match _repeaters[repno].aux_forward(&drtioaux::Packet::DestinationStatusRequest {
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destination: _destination
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}, timer) {
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Ok(()) => (),
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Err(drtioaux::Error::LinkDown) => drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?,
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Err(e) => {
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drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
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error!("aux error when handling destination status request: {:?}", e);
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},
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}
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} else {
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drtioaux::send(0, &drtioaux::Packet::DestinationDownReply)?;
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}
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}
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}
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Ok(())
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}
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#[cfg(has_drtio_routing)]
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drtioaux::Packet::RoutingSetPath { destination, hops } => {
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_routing_table.0[destination as usize] = hops;
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for rep in _repeaters.iter() {
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if let Err(e) = rep.set_path(destination, &hops, timer) {
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error!("failed to set path ({:?})", e);
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}
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}
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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#[cfg(has_drtio_routing)]
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drtioaux::Packet::RoutingSetRank { rank } => {
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*_rank = rank;
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drtio_routing::interconnect_enable_all(_routing_table, rank);
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let rep_rank = rank + 1;
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for rep in _repeaters.iter() {
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if let Err(e) = rep.set_rank(rep_rank, timer) {
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error!("failed to set rank ({:?})", e);
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}
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}
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info!("rank: {}", rank);
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info!("routing table: {}", _routing_table);
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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#[cfg(not(has_drtio_routing))]
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drtioaux::Packet::RoutingSetPath { destination: _, hops: _ } => {
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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#[cfg(not(has_drtio_routing))]
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drtioaux::Packet::RoutingSetRank { rank: _ } => {
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drtioaux::send(0, &drtioaux::Packet::RoutingAck)
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}
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drtioaux::Packet::MonitorRequest { destination: _destination, channel: _channel, probe: _probe } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let value;
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#[cfg(has_rtio_moninj)]
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unsafe {
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csr::rtio_moninj::mon_chan_sel_write(channel as _);
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csr::rtio_moninj::mon_probe_sel_write(probe);
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csr::rtio_moninj::mon_value_update_write(1);
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value = csr::rtio_moninj::mon_value_read();
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}
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#[cfg(not(has_rtio_moninj))]
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{
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value = 0;
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}
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let reply = drtioaux::Packet::MonitorReply { value: value as u32 };
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drtioaux::send(0, &reply)
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},
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drtioaux::Packet::InjectionRequest { destination: _destination, channel: _channel,
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overrd: _overrd, value: _value } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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#[cfg(has_rtio_moninj)]
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unsafe {
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csr::rtio_moninj::inj_chan_sel_write(channel as _);
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csr::rtio_moninj::inj_override_sel_write(overrd);
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csr::rtio_moninj::inj_value_write(value);
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}
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Ok(())
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},
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drtioaux::Packet::InjectionStatusRequest { destination: _destination,
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channel: _channel, overrd: _overrd } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let value;
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#[cfg(has_rtio_moninj)]
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unsafe {
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csr::rtio_moninj::inj_chan_sel_write(channel as _);
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csr::rtio_moninj::inj_override_sel_write(overrd);
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value = csr::rtio_moninj::inj_value_read();
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}
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#[cfg(not(has_rtio_moninj))]
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{
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value = 0;
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}
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drtioaux::send(0, &drtioaux::Packet::InjectionStatusReply { value: value })
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},
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drtioaux::Packet::I2cStartRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = i2c.start().is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cRestartRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = i2c.restart().is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cStopRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = i2c.stop().is_ok();
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drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
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}
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drtioaux::Packet::I2cWriteRequest { destination: _destination, busno: _busno, data } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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match i2c.write(data) {
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Ok(ack) => drtioaux::send(0,
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&drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
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Err(_) => drtioaux::send(0,
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&drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false })
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}
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}
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drtioaux::Packet::I2cReadRequest { destination: _destination, busno: _busno, ack } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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match i2c.read(ack) {
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Ok(data) => drtioaux::send(0,
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&drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
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Err(_) => drtioaux::send(0,
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&drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
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}
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}
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drtioaux::Packet::SpiSetConfigRequest { destination: _destination, busno: _busno,
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flags: _flags, length: _length, div: _div, cs: _cs } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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// todo: reimplement when/if SPI is available
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//let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::SpiBasicReply { succeeded: false })
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},
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drtioaux::Packet::SpiWriteRequest { destination: _destination, busno: _busno, data: _data } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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// todo: reimplement when/if SPI is available
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//let succeeded = spi::write(busno, data).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::SpiBasicReply { succeeded: false })
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}
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drtioaux::Packet::SpiReadRequest { destination: _destination, busno: _busno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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// todo: reimplement when/if SPI is available
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// match spi::read(busno) {
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// Ok(data) => drtioaux::send(0,
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// &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
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// Err(_) => drtioaux::send(0,
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// &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
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// }
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drtioaux::send(0,
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&drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
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}
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_ => {
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warn!("received unexpected aux packet");
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Ok(())
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}
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}
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}
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fn process_aux_packets(repeaters: &mut [repeater::Repeater],
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routing_table: &mut drtio_routing::RoutingTable, rank: &mut u8,
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timer: &mut GlobalTimer, i2c: &mut I2c) {
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let result =
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drtioaux::recv(0).and_then(|packet| {
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if let Some(packet) = packet {
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process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c)
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} else {
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Ok(())
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}
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});
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match result {
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Ok(()) => (),
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Err(e) => warn!("aux packet error ({:?})", e)
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}
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}
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fn drtiosat_process_errors() {
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let errors;
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unsafe {
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errors = csr::drtiosat::protocol_error_read();
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}
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if errors & 1 != 0 {
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error!("received packet of an unknown type");
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}
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if errors & 2 != 0 {
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error!("received truncated packet");
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}
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if errors & 4 != 0 {
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let destination;
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unsafe {
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destination = csr::drtiosat::buffer_space_timeout_dest_read();
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}
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error!("timeout attempting to get buffer space from CRI, destination=0x{:02x}", destination)
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}
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if errors & 8 != 0 {
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let channel;
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let timestamp_event;
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let timestamp_counter;
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unsafe {
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channel = csr::drtiosat::underflow_channel_read();
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timestamp_event = csr::drtiosat::underflow_timestamp_event_read() as i64;
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timestamp_counter = csr::drtiosat::underflow_timestamp_counter_read() as i64;
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}
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error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
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channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
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}
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if errors & 16 != 0 {
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error!("write overflow");
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}
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unsafe {
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csr::drtiosat::protocol_error_write(errors);
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}
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}
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#[cfg(has_rtio_crg)]
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fn init_rtio_crg(timer: GlobalTimer) {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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timer.delay_us(150);
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let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
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if !locked {
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error!("RTIO clock failed");
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}
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}
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#[cfg(not(has_rtio_crg))]
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fn init_rtio_crg(_timer: GlobalTimer) { }
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fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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let now = timer.get_time();
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let mut ts_ms = Milliseconds(*ts);
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if now > ts_ms {
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ts_ms = now + Milliseconds(200);
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*ts = ts_ms.0;
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}
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}
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#[cfg(has_si5324)]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: true
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};
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static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
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#[no_mangle]
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pub extern fn main_core0() -> i32 {
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enable_l2_cache(0x8);
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let mut timer = GlobalTimer::start();
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let buffer_logger = unsafe {
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logger::BufferLogger::new(&mut LOG_BUFFER[..])
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};
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buffer_logger.set_uart_log_level(log::LevelFilter::Info);
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buffer_logger.register();
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log::set_max_level(log::LevelFilter::Info);
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init_gateware();
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info!("ARTIQ satellite manager starting...");
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info!("gateware ident {}", identifier_read(&mut [0; 64]));
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ram::init_alloc_core0();
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let mut i2c = I2c::i2c0();
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i2c.init().expect("I2C initialization failed");
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#[cfg(has_si5324)]
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si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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timer.delay_us(1500); // wait for CPLL/QPLL lock
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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init_rtio_crg(timer);
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#[cfg(has_drtio_routing)]
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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#[cfg(not(has_drtio_routing))]
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let mut repeaters = [repeater::Repeater::default(); 0];
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for i in 0..repeaters.len() {
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repeaters[i] = repeater::Repeater::new(i as u8);
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}
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let mut routing_table = drtio_routing::RoutingTable::default_empty();
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let mut rank = 1;
|
|
|
|
let mut hardware_tick_ts = 0;
|
|
|
|
loop {
|
|
while !drtiosat_link_rx_up() {
|
|
drtiosat_process_errors();
|
|
#[allow(unused_mut)]
|
|
for mut rep in repeaters.iter_mut() {
|
|
rep.service(&routing_table, rank, &mut timer);
|
|
}
|
|
hardware_tick(&mut hardware_tick_ts, &mut timer);
|
|
}
|
|
|
|
info!("uplink is up, switching to recovered clock");
|
|
#[cfg(has_siphaser)]
|
|
{
|
|
si5324::siphaser::select_recovered_clock(&mut i2c, true, &mut timer).expect("failed to switch clocks");
|
|
si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
|
|
}
|
|
|
|
drtioaux::reset(0);
|
|
drtiosat_reset(false);
|
|
drtiosat_reset_phy(false);
|
|
|
|
while drtiosat_link_rx_up() {
|
|
drtiosat_process_errors();
|
|
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c);
|
|
#[allow(unused_mut)]
|
|
for mut rep in repeaters.iter_mut() {
|
|
rep.service(&routing_table, rank, &mut timer);
|
|
}
|
|
hardware_tick(&mut hardware_tick_ts, &mut timer);
|
|
if drtiosat_tsc_loaded() {
|
|
info!("TSC loaded from uplink");
|
|
for rep in repeaters.iter() {
|
|
if let Err(e) = rep.sync_tsc(&mut timer) {
|
|
error!("failed to sync TSC ({:?})", e);
|
|
}
|
|
}
|
|
if let Err(e) = drtioaux::send(0, &drtioaux::Packet::TSCAck) {
|
|
error!("aux packet error: {:?}", e);
|
|
}
|
|
}
|
|
}
|
|
|
|
drtiosat_reset_phy(true);
|
|
drtiosat_reset(true);
|
|
drtiosat_tsc_loaded();
|
|
info!("uplink is down, switching to local oscillator clock");
|
|
#[cfg(has_siphaser)]
|
|
si5324::siphaser::select_recovered_clock(&mut i2c, false, &mut timer).expect("failed to switch clocks");
|
|
}
|
|
}
|
|
|
|
extern "C" {
|
|
static mut __stack1_start: u32;
|
|
}
|
|
|
|
interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
|
|
if MPIDR.read().cpu_id() == 1{
|
|
let mpcore = mpcore::RegisterBlock::mpcore();
|
|
let mut gic = gic::InterruptController::gic(mpcore);
|
|
let id = gic.get_interrupt_id();
|
|
if id.0 == 0 {
|
|
gic.end_interrupt(id);
|
|
asm::exit_irq();
|
|
SP.write(&mut __stack1_start as *mut _ as u32);
|
|
asm::enable_irq();
|
|
CORE1_RESTART.store(false, Ordering::Relaxed);
|
|
notify_spin_lock();
|
|
main_core1();
|
|
}
|
|
stdio::drop_uart();
|
|
}
|
|
loop {}
|
|
});
|
|
|
|
static mut PANICKED: [bool; 2] = [false; 2];
|
|
|
|
static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
|
|
|
|
pub fn restart_core1() {
|
|
let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
|
|
CORE1_RESTART.store(true, Ordering::Relaxed);
|
|
interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
|
|
while CORE1_RESTART.load(Ordering::Relaxed) {
|
|
spin_lock_yield();
|
|
}
|
|
}
|
|
|
|
#[no_mangle]
|
|
pub fn main_core1() {
|
|
let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
|
|
interrupt_controller.enable_interrupts();
|
|
|
|
loop {}
|
|
}
|
|
|
|
#[no_mangle]
|
|
pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) {
|
|
|
|
fn hexdump(addr: u32) {
|
|
let addr = (addr - addr % 4) as *const u32;
|
|
let mut ptr = addr;
|
|
println!("@ {:08p}", ptr);
|
|
for _ in 0..4 {
|
|
print!("+{:04x}: ", ptr as usize - addr as usize);
|
|
print!("{:08x} ", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
print!("{:08x} ", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
print!("{:08x} ", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
print!("{:08x}\n", unsafe { *ptr }); ptr = ptr.wrapping_offset(1);
|
|
}
|
|
}
|
|
|
|
hexdump(pc);
|
|
hexdump(ea);
|
|
panic!("exception at PC 0x{:x}, EA 0x{:x}", pc, ea)
|
|
}
|
|
|
|
#[no_mangle] // https://github.com/rust-lang/rust/issues/{38281,51647}
|
|
#[panic_handler]
|
|
pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
|
|
let id = MPIDR.read().cpu_id() as usize;
|
|
print!("Core {} ", id);
|
|
unsafe {
|
|
if PANICKED[id] {
|
|
println!("nested panic!");
|
|
loop {}
|
|
}
|
|
PANICKED[id] = true;
|
|
}
|
|
print!("panic at ");
|
|
if let Some(location) = info.location() {
|
|
print!("{}:{}:{}", location.file(), location.line(), location.column());
|
|
} else {
|
|
print!("unknown location");
|
|
}
|
|
if let Some(message) = info.message() {
|
|
println!(": {}", message);
|
|
} else {
|
|
println!("");
|
|
}
|
|
|
|
|
|
loop {}
|
|
}
|
|
|
|
// linker symbols
|
|
extern "C" {
|
|
static __text_start: u32;
|
|
static __text_end: u32;
|
|
static __exidx_start: u32;
|
|
static __exidx_end: u32;
|
|
}
|
|
|
|
#[no_mangle]
|
|
extern fn dl_unwind_find_exidx(_pc: *const u32, len_ptr: *mut u32) -> *const u32 {
|
|
let length;
|
|
let start: *const u32;
|
|
unsafe {
|
|
length = (&__exidx_end as *const u32).offset_from(&__exidx_start) as u32;
|
|
start = &__exidx_start;
|
|
*len_ptr = length;
|
|
}
|
|
start
|
|
}
|