449 lines
14 KiB
Rust
449 lines
14 KiB
Rust
use embedded_hal::blocking::delay::DelayMs;
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#[cfg(has_si5324)]
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use ksupport::i2c;
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use libboard_artiq::pl;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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#[cfg(has_si549)]
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use libboard_artiq::si549;
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#[cfg(has_si5324)]
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use libboard_zynq::i2c::I2c;
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use libboard_zynq::timer::GlobalTimer;
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use libconfig::Config;
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use log::{info, warn};
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[allow(non_camel_case_types)]
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pub enum RtioClock {
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Default,
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Int_125,
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Int_100,
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Int_150,
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Ext0_Bypass,
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Ext0_Synth0_10to125,
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Ext0_Synth0_80to125,
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Ext0_Synth0_100to125,
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Ext0_Synth0_125to125,
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}
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#[allow(unreachable_code)]
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fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
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let mut res = RtioClock::Default;
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if let Ok(clk) = cfg.read_str("rtio_clock") {
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res = match clk.as_ref() {
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"int_125" => RtioClock::Int_125,
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"int_100" => RtioClock::Int_100,
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"int_150" => RtioClock::Int_150,
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"ext0_bypass" => RtioClock::Ext0_Bypass,
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"ext0_bypass_125" => RtioClock::Ext0_Bypass,
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"ext0_bypass_100" => RtioClock::Ext0_Bypass,
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"ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125,
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"ext0_synth0_80to125" => RtioClock::Ext0_Synth0_80to125,
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"ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125,
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"ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
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_ => {
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warn!("Unrecognised rtio_clock setting. Falling back to default.");
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RtioClock::Default
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}
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};
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} else {
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warn!("error reading configuration. Falling back to default.");
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}
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if res == RtioClock::Default {
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#[cfg(rtio_frequency = "100.0")]
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{
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warn!("Using default configuration - internal 100MHz RTIO clock.");
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return RtioClock::Int_100;
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}
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#[cfg(rtio_frequency = "125.0")]
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{
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warn!("Using default configuration - internal 125MHz RTIO clock.");
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return RtioClock::Int_125;
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}
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// anything else
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{
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warn!("Using default configuration - internal 125MHz RTIO clock.");
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return RtioClock::Int_125;
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}
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}
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res
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}
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#[cfg(not(has_drtio))]
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fn init_rtio(timer: &mut GlobalTimer) {
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info!("Switching SYS clocks...");
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unsafe {
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pl::csr::sys_crg::clock_switch_write(1);
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}
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// if it's not locked, it will hang at the CSR.
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timer.delay_ms(50); // wait for CPLL/QPLL/SYS PLL lock
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let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
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if clk == 1 {
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info!("SYS CLK switched successfully");
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} else {
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panic!("SYS CLK did not switch");
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}
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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}
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info!("SYS PLL locked");
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}
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#[cfg(has_drtio)]
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fn init_drtio(timer: &mut GlobalTimer) {
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unsafe {
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pl::csr::gt_drtio::stable_clkin_write(1);
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}
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timer.delay_ms(50); // wait for CPLL/QPLL/SYS PLL lock
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let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
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if clk == 1 {
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info!("SYS CLK switched successfully");
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} else {
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panic!("SYS CLK did not switch");
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}
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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pl::csr::gt_drtio::txenable_write(0xffffffffu32 as _);
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#[cfg(has_drtio_eem)]
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pl::csr::eem_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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// Si5324 input to select for locking to an external clock.
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#[cfg(has_si5324)]
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const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1;
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#[cfg(has_si5324)]
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fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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let (si5324_settings, si5324_ref_input) = match clk {
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RtioClock::Ext0_Synth0_10to125 => {
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// 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs: 10,
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nc1_ls: 4,
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n2_hs: 10,
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n2_ls: 300,
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n31: 6,
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n32: 6,
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bwsel: 4,
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crystal_as_ckin2: false,
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},
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SI5324_EXT_INPUT,
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)
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}
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RtioClock::Ext0_Synth0_80to125 => {
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// 125 MHz output from 80 MHz CLKINx reference, 611 Hz BW
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info!("using 80MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs: 4,
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nc1_ls: 10,
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n2_hs: 10,
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n2_ls: 250,
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n31: 40,
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n32: 40,
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bwsel: 4,
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crystal_as_ckin2: false,
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},
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SI5324_EXT_INPUT,
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)
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}
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RtioClock::Ext0_Synth0_100to125 => {
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// 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs: 10,
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nc1_ls: 4,
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n2_hs: 10,
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n2_ls: 260,
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n31: 52,
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n32: 52,
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bwsel: 4,
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crystal_as_ckin2: false,
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},
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SI5324_EXT_INPUT,
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)
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}
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RtioClock::Ext0_Synth0_125to125 => {
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// 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs: 5,
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nc1_ls: 8,
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n2_hs: 7,
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n2_ls: 360,
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n31: 63,
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n32: 63,
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bwsel: 4,
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crystal_as_ckin2: false,
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},
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SI5324_EXT_INPUT,
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)
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}
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RtioClock::Int_150 => {
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// 150MHz output, from crystal
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info!("using internal 150MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs: 9,
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nc1_ls: 4,
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n2_hs: 10,
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n2_ls: 33732,
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n31: 7139,
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n32: 7139,
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bwsel: 3,
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crystal_as_ckin2: true,
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},
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si5324::Input::Ckin2,
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)
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}
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RtioClock::Int_100 => {
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// 100MHz output, from crystal
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info!("using internal 100MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs: 9,
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nc1_ls: 6,
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n2_hs: 10,
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n2_ls: 33732,
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n31: 7139,
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n32: 7139,
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bwsel: 3,
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crystal_as_ckin2: true,
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},
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si5324::Input::Ckin2,
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)
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}
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RtioClock::Int_125 => {
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// 125MHz output, from crystal, 7 Hz
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info!("using internal 125MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs: 10,
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nc1_ls: 4,
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n2_hs: 10,
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n2_ls: 19972,
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n31: 4565,
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n32: 4565,
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bwsel: 4,
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crystal_as_ckin2: true,
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},
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si5324::Input::Ckin2,
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)
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}
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_ => {
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// same setting as Int_125, but fallback to default
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warn!(
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"rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.",
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clk
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);
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(
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si5324::FrequencySettings {
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n1_hs: 10,
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nc1_ls: 4,
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n2_hs: 10,
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n2_ls: 19972,
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n31: 4565,
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n32: 4565,
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bwsel: 4,
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crystal_as_ckin2: true,
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},
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si5324::Input::Ckin2,
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)
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}
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};
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si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
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}
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#[cfg(all(has_si549, has_wrpll))]
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fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::FrequencySetting) {
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// register values are directly copied from preconfigured mmcm
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let (mmcm_setting, mmcm_bypass) = match clk {
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RtioClock::Ext0_Synth0_10to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 62.5, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 5
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clkout0_reg1: 0x1083,
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clkout0_reg2: 0x0080,
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clkfbout_reg1: 0x179e,
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clkfbout_reg2: 0x4c00,
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div_reg: 0x1041,
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lock_reg1: 0x00fa,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg2: 0x0800,
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},
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false,
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),
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RtioClock::Ext0_Synth0_80to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 15.625, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 10
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clkout0_reg1: 0x1145,
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clkout0_reg2: 0x0000,
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clkfbout_reg1: 0x11c7,
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clkfbout_reg2: 0x5880,
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div_reg: 0x1041,
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lock_reg1: 0x028a,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg2: 0x9800,
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},
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false,
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),
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RtioClock::Ext0_Synth0_100to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 12.5, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 10
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clkout0_reg1: 0x1145,
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clkout0_reg2: 0x0000,
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clkfbout_reg1: 0x1145,
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clkfbout_reg2: 0x4c00,
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div_reg: 0x1041,
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lock_reg1: 0x0339,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg2: 0x9800,
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},
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false,
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),
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RtioClock::Ext0_Synth0_125to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 10
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clkout0_reg1: 0x1145,
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clkout0_reg2: 0x0000,
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clkfbout_reg1: 0x1145,
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clkfbout_reg2: 0x0000,
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div_reg: 0x1041,
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lock_reg1: 0x03e8,
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lock_reg2: 0x7001,
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lock_reg3: 0xf3e9,
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power_reg: 0x0100,
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filt_reg1: 0x0808,
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filt_reg2: 0x1100,
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},
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true,
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),
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_ => unreachable!(),
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};
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si549::helper_setup(timer, &si549_settings).expect("cannot initialize helper Si549");
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si549::wrpll_refclk::setup(timer, mmcm_setting, mmcm_bypass).expect("cannot initialize ref clk for wrpll");
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si549::wrpll::select_recovered_clock(true, timer);
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}
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#[cfg(has_si549)]
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fn get_si549_setting(clk: RtioClock) -> si549::FrequencySetting {
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match clk {
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RtioClock::Ext0_Synth0_10to125 => {
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info!("using 10MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Ext0_Synth0_80to125 => {
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info!("using 80MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Ext0_Synth0_100to125 => {
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info!("using 100MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Ext0_Synth0_125to125 => {
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info!("using 125MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Int_100 => {
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info!("using internal 100MHz RTIO clock");
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}
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RtioClock::Int_125 => {
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info!("using internal 125MHz RTIO clock");
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}
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_ => {
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warn!(
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"rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.",
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clk
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);
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}
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};
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match clk {
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RtioClock::Int_100 => {
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si549::FrequencySetting {
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main: si549::DividerConfig {
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hsdiv: 0x06C,
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lsdiv: 0,
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fbdiv: 0x046C5F49797,
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},
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helper: si549::DividerConfig {
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// 100MHz*32767/32768
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hsdiv: 0x06C,
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lsdiv: 0,
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fbdiv: 0x046C5670BBD,
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},
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}
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}
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_ => {
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// Everything else use 125MHz
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si549::FrequencySetting {
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main: si549::DividerConfig {
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hsdiv: 0x058,
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lsdiv: 0,
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fbdiv: 0x04815791F25,
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},
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helper: si549::DividerConfig {
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// 125MHz*32767/32768
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hsdiv: 0x058,
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lsdiv: 0,
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fbdiv: 0x04814E8F442,
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},
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}
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}
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}
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}
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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let clk = get_rtio_clock_cfg(cfg);
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#[cfg(has_si5324)]
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{
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let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
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match clk {
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RtioClock::Ext0_Bypass => {
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info!("bypassing the PLL for RTIO clock");
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si5324::bypass(i2c, SI5324_EXT_INPUT, timer).expect("cannot bypass Si5324")
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}
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_ => setup_si5324(i2c, timer, clk),
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}
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}
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#[cfg(has_si549)]
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let si549_settings = get_si549_setting(clk);
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#[cfg(has_si549)]
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si549::main_setup(timer, &si549_settings).expect("cannot initialize main Si549");
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#[cfg(has_drtio)]
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init_drtio(timer);
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#[cfg(not(has_drtio))]
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init_rtio(timer);
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#[cfg(all(has_si549, has_wrpll))]
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{
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// SYS CLK switch will reset CSRs that are used by WRPLL
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match clk {
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RtioClock::Ext0_Synth0_10to125
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| RtioClock::Ext0_Synth0_80to125
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| RtioClock::Ext0_Synth0_100to125
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| RtioClock::Ext0_Synth0_125to125 => {
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wrpll_setup(timer, clk, &si549_settings);
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}
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_ => {}
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}
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}
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}
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